Stacked Image Sensor Structure for Parallel Readout and Wafer Bonding
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Solution Overview
Problem
Current image sensors face challenges in achieving high dynamic range and efficient light capture due to limitations in pixel size, alignment issues during stacking, and the sequential shifting of image information in CCD technology, which affects light sensitivity and speed.
Innovation Solution
The use of layer transfer technology to monolithically stack photodetectors and read-out circuits, allowing for parallel data collection and the integration of multiple photodetector layers with varying light-sensitive areas, and the implementation of two image sensor arrays with distinct distances from the lens for enhanced light detection and image reconstruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential shifting is used to transfer image information in CCD technology, then device complexity is reduced, but light sensitivity and processing speed deteriorate
Solution Approach 1:
The patent transitions from sequential one-dimensional shifting to parallel three-dimensional stacked architecture, where multiple photodetector layers are vertically stacked above read-out circuits. This dimensional change enables simultaneous data collection from multiple layers, dramatically increasing processing speed while maintaining manageable device complexity through standardized bonding interfaces.
Solution Approach 2:
The patent divides the image sensor into separate functional layers: photodetector layers for light detection and read-out circuit layers for data processing. These segmented layers are stacked vertically and bonded together, allowing parallel operation of multiple photodetector arrays simultaneously, thus improving processing speed without proportionally increasing overall device complexity.
2Area of stationary object
If pixel size is reduced to increase sensor density, then area coverage is improved, but alignment precision during stacking deteriorates
Solution Approach 1:
The patent incorporates alignment marks and positioning structures during the preliminary fabrication stages of each layer before stacking. These pre-established reference features enable precise alignment during the bonding process, ensuring that even sub-10-micron pixels can be accurately registered across multiple stacked layers without compromising manufacturing precision.
Solution Approach 2:
The patent introduces intermediary alignment marks and positioning structures as mediating elements between the photodetector layers and read-out circuit layers. These intermediaries provide reference points that facilitate accurate alignment during stacking, enabling high-precision assembly even when pixel dimensions are reduced to increase sensor area coverage.
3Reliability
If multiple photodetector layers are stacked to enhance light sensitivity, then light detection capability is improved, but device complexity increases
Solution Approach 1:
The patent stacks multiple photodetector layers vertically in the third dimension above the read-out circuits, rather than expanding horizontally. This vertical stacking enables enhanced light sensitivity through multiple detection layers while maintaining a compact footprint and managing device complexity through standardized bonding interfaces and integrated circuit design.
Solution Approach 2:
The patent merges multiple photodetector layers with read-out circuit layers into a single integrated stacked device. By combining these functional layers through bonding, the patent achieves enhanced light sensitivity from multiple photodetectors while consolidating the overall device structure, thereby managing complexity through integration rather than separate components.
4Reliability
If through-silicon via technology is used for alignment, then connection reliability is improved, but manufacturing complexity and time increase
Solution Approach 1:
The patent applies alignment marks and positioning structures at critical interfaces between stacked layers, rather than attempting to control alignment across the entire device. This partial application of alignment features at key bonding interfaces achieves sufficient connection reliability while avoiding the excessive manufacturing complexity and time that would result from comprehensive alignment control throughout the entire device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves light sensitivity, reduces pixel size limitations, enables parallel data processing, and enhances dynamic range, resulting in more efficient image capture and reconstruction with reduced alignment errors and increased speed.
Implementation Method 1
wherein said second level is bonded to said first level, and wherein said bonded comprises an oxide to oxide bond
Data Source
AI summary
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of memory circuits.