Image Sensor Output Timing to Distribute Peak Current

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Solution Overview

Problem

Conventional CMOS image sensors experience transient peak currents when outputting digital signals, which can lead to voltage drops and affect high-speed circuits like analog-to-digital converters, particularly in high-resolution imaging applications.

Innovation Solution

The image sensor employs multiple analog-to-digital converters and output circuits with independent enable control signals, allowing for staggered output of bit values to distribute peak current, reducing the risk of voltage drops by controlling the timing of enable signals for each pixel row.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If digital signals corresponding to column lines are output to buffers at the same time, then high-speed processing is achieved, but transient peak current occurs causing voltage drop

Engineering Contradiction:
Improvesignal processing speedVSAvoidvoltage stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent segments the simultaneous output operation into multiple sequential output operations. Different pixel rows are divided into groups, and digital signals from different groups are output at different time periods. This segmentation distributes the peak current across multiple time slots while maintaining high-speed processing capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the output timing of digital signals from different pixel rows. By controlling output circuits to sequentially output signals from different row groups at different time periods, the system adapts the output schedule to distribute current demand, preventing simultaneous peak current while preserving overall processing speed.

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple analog-to-digital converters output bit values simultaneously, then processing throughput is improved, but peak current increases causing voltage drop

Engineering Contradiction:
Improvesignal processing throughputVSAvoidvoltage stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the simultaneous output operation into multiple sequential output operations. Different pixel rows are divided into groups, and digital signals from different groups are output at different time periods. This segmentation distributes the peak current across multiple time slots while maintaining high-speed processing capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic action by outputting digital signals from different pixel row groups in alternating time periods. First pixel rows output in one period, second pixel rows output in the next period, creating a periodic pattern that distributes current demand over time while maintaining continuous high throughput.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9819891B2Image sensor for distributing output peak current and image processing system including the same
Publication Date: 2017.11.14 SAMSUNG ELECTRONICS CO LTD
  • US9819891B2 patent drawing
  • US9819891B2 patent drawing
  • US9819891B2 patent drawing

AI summary

The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.