Image Sensor Column Pipeline Noise Compensation
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Solution Overview
Problem
High-resolution CMOS image sensors face manufacturing yield issues due to noise problems associated with pixel power supply circuitry and column fixed pattern noise (CFPN) caused by decreased unit pixel size, leading to image quality deterioration and increased defective sensor identification.
Innovation Solution
An image sensor system that includes a switch signal generator to identify and compensate for fixed pattern noise by selectively activating or deactivating column-parallel pipelines based on noise location information, using a binning switch block to perform digital binning on signals from noise-free pipelines, thereby reducing CFPN and improving image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If unit pixel size is decreased to achieve high resolution, then image resolution is improved, but manufacturing yield deteriorates due to noise issues and defective pixels
Solution Approach 1:
The patent changes the operational parameters of column pipelines by dynamically adjusting which pipelines are active based on noise characteristics. Instead of using all pipelines uniformly, the system identifies noisy pipelines and modifies their operational status, thereby improving image quality without requiring larger pixel sizes
Solution Approach 2:
The patent extracts and removes noisy column pipelines from the active imaging process. By identifying pipelines with high fixed pattern noise and excluding them from contributing to the final image, the system effectively removes the harmful elements while maintaining the high resolution structure
2Measurement precision
If unit pixel size is decreased to achieve high resolution, then image resolution is improved, but fixed pattern noise increases leading to image quality deterioration
Solution Approach 1:
The system changes the operational parameters of column pipelines by dynamically adjusting which pipelines are active based on their noise characteristics. Noisy pipelines are identified and their operational status is modified, thereby reducing fixed pattern noise while maintaining high resolution
Solution Approach 2:
The patent converts the harmful effect of fixed pattern noise into a beneficial selection criterion. By measuring and identifying which pipelines exhibit high noise, the system uses this information to selectively activate only the quiet pipelines, thereby transforming the noise measurement into a quality control mechanism
3Area of stationary object
If ADC capacitor area is decreased to accommodate high resolution, then chip area efficiency is improved, but column fixed pattern noise increases due to impedance mismatching
Solution Approach 1:
The patent changes the operational configuration of column pipelines based on their noise characteristics. By identifying pipelines with impedance mismatching issues and excluding them from active imaging, the system reduces column fixed pattern noise while maintaining efficient chip area utilization
Solution Approach 2:
The system extracts and removes problematic column pipelines from the active imaging process. By identifying pipelines with impedance mismatching and excluding them, the harmful effects of small ADC capacitor area are mitigated without requiring larger capacitors
Data Source
AI summary
An image sensor operating in a skip mode and reading out a pixel signal provided by at least one of a plurality of pixels and compensating for fixed pattern noise (FPN) in column-parallel pipelines. The image sensor includes; a switch signal generator that generates a first switch control signal and a second switch control signal in response to FPN location information characterizing a first pipeline among the column-parallel pipelines as a noisy pipeline generating FPN, and characterizing a second pipeline among the column-parallel pipelines as a quiet pipeline not generating FPN, a binning switch block including a first switch controlled by the first switch control signal and a second switch controlled by the second switch control signal, wherein the first switch control signal causes the first pipeline to be inactivated and the second switch control signal causes the second pipeline to be activated, and a binning block that performs a digital binning operation on digital signals provided via the column-parallel pipelines including the second pipeline.