3D Stacked Image Sensor Layout for Pixel Array Area Limits
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Solution Overview
Problem
Current image sensors face challenges in optimizing pixel array size relative to die size, often sacrificing image quality due to space constraints and increased complexity of on-chip analog-to-digital conversion and signal processing, which limits the ratio of pixel array size to die size and increases manufacturing costs.
Innovation Solution
The solution involves a three-dimensional stacking technology where the pixel array is separated from supporting circuitry, with the latter being located on one or more additional substrates, allowing for a more vertical configuration and increased pixel array size while maintaining high image quality, using interconnects like wirebonds, bumps, or TSVs for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pixel array size is increased on a single chip, then more data can be captured, but the area available for A/D conversion and signal processing circuitry decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. The pixel array is placed on a first substrate while A/D conversion and signal processing circuitry are placed on a second substrate, utilizing the vertical dimension to resolve the area conflict between pixel array and supporting circuitry.
Solution Approach 2:
The image sensor is divided into separate functional modules on different substrates: the pixel array on the first substrate and the supporting circuitry (A/D converters, amplifiers, filters) on the second substrate. This segmentation allows each module to be optimized independently and connected through interconnects.
2Adaptability or versatility
If more circuitry is integrated on the same chip, then signal processing capability improves, but manufacturing precision requirements increase due to smaller contact pads
Solution Approach 1:
By moving supporting circuitry to a second substrate in the vertical dimension, the patent eliminates the need for increasingly smaller contact pads on a single chip. The interconnects between substrates provide robust electrical connections without the manufacturing precision constraints of miniaturized on-chip contact pads.
3Area of moving object
If a three-dimensional stacked architecture is used, then pixel array size can be increased, but device complexity increases due to additional substrates and interconnects
Solution Approach 1:
The image sensor is divided into separate functional modules on different substrates: the pixel array on the first substrate and the supporting circuitry (A/D converters, amplifiers, filters) on the second substrate. This segmentation allows each module to be optimized independently and connected through interconnects.
4Measurement precision
If the pixel array occupies most of the die area, then image quality improves, but the ratio of pixel array size to die size is limited by on-chip circuitry space
Solution Approach 1:
The patent utilizes the vertical dimension by stacking substrates, allowing the pixel array on the first substrate to occupy nearly the entire die area without sacrificing space for supporting circuitry, which are placed on a second substrate. This dramatically increases the pixel array to die area ratio.
Data Source
AI summary
An imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.