Image Sensor Pixel Group Node Sharing for Compact Dual Conversion Gain
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Solution Overview
Problem
Image sensors face challenges in miniaturization due to the physical size of elements and design rule limitations, making it difficult to increase pixel density and support dual conversion gain (DCG) functions, which hinders their compactness and functionality in smaller devices.
Innovation Solution
The design includes a configuration where multiple photodiodes share nodes connected to capacitors and transistors, allowing for efficient use of chip space by reducing the number of transistors and metal contacts, enabling the DCG function even in small pixels, and dynamically adjusting capacitance for high and low conversion gain modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a larger quantity of pixels is included to increase resolution, then image quality is improved, but pixel size must be reduced which increases layout complexity and makes miniaturization difficult due to design rule limitations
Solution Approach 1:
Multiple photodiodes (first photodiodes and second photodiodes) share common nodes (first node and second node) and common transistors (reset transistors and common transistor), reducing the total number of discrete elements and simplifying layout while maintaining high pixel density
Solution Approach 2:
The common transistor serves multiple functions by selectively connecting different nodes (first node, second node, third node) to the pixel voltage node, and the reset transistors collectively manage electrical connections between multiple nodes, enabling a single element to perform multiple operational roles
2Measurement precision
If pixel size is reduced to increase pixel density, then resolution is improved, but the physical size of elements (transistors, capacitors, metal contacts) makes miniaturization difficult due to design rule limitations
Solution Approach 1:
Multiple photodiodes share common nodes and common transistors, significantly reducing the number of individual elements that need to be miniaturized, thereby enabling smaller pixel sizes while maintaining functionality and adhering to design rules
Solution Approach 2:
The patent utilizes vertical stacking and multi-layer interconnect structures to accommodate shared nodes and transistors in three-dimensional space, effectively reducing the two-dimensional footprint of each pixel element
3Adaptability or versatility
If dual conversion gain function is supported in small pixels, then functionality is improved, but layout complexity increases
Solution Approach 1:
The common transistor and reset transistors are configured to dynamically connect different nodes (first node, second node, third node) to the pixel voltage node, enabling the pixel to switch between high conversion gain and low conversion gain modes using the same shared infrastructure, thus achieving dual functionality without proportionally increasing layout complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the compactness of image sensors, allowing them to be integrated into smaller devices with increased functionality and performance, while reducing layout complexity and noise, and improving object recognition in varying luminance conditions.
Implementation Method 1
Image sensors may convert one or more optical signals received at the image sensors, where the one or more optical signals may include information associated with one or more images of one or more subjects, into one or more electrical signals
Data Source
AI summary
An image sensor includes first photodiodes sharing a first node that is connected to a first capacitor, second photodiodes sharing a second node that is connected to a second capacitor, a common transistor configured to selectively connect a third node to a pixel voltage node, the third node connected to a third capacitor, a first reset transistor that may selectively connect the first node to the third node, and a second reset transistor that may selectively connect the second node to the third node. The first reset transistor and the second reset transistor may electrically connect the first node, the second node, and the third node to each other according to an operation of the first reset transistor and the second reset transistor. The common transistor is configured to reset the third node to the pixel voltage according to an operation of the common transistor.