CMOS Image Sensor Pixel Isolation for Higher QE and Lower Crosstalk
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Solution Overview
Problem
Existing CMOS image sensors face challenges in maintaining sufficient quantum efficiency (QE) and adequate electrical isolation as pixel size shrinks, leading to reduced performance and increased crosstalk among adjacent pixels.
Innovation Solution
The implementation of photodetectors separated by metal isolation features with a metal grid and negative bias application, which serve as reflectors and improve electrical isolation, enhancing QE and reducing crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel size is shrunk to increase resolution, then productivity and production efficiency are improved, but quantum efficiency deteriorates and crosstalk increases
Solution Approach 1:
The patent introduces deep trench isolation structures that segment the semiconductor substrate into isolated pixel regions. These trenches extend deeply into the substrate, creating physical and electrical separation between adjacent pixels, thereby preventing crosstalk while maintaining small pixel dimensions for high resolution.
Solution Approach 2:
The patent employs metal isolation features as intermediary elements positioned between adjacent photodetectors. These metal structures serve as reflectors that redirect incident light toward the photodetector active areas, improving quantum efficiency by reducing light loss at pixel boundaries while maintaining electrical isolation.
2Productivity
If pixel size is shrunk to increase resolution, then productivity and production efficiency are improved, but electrical isolation deteriorates leading to increased crosstalk
Solution Approach 1:
The deep trench isolation structures segment the semiconductor substrate into isolated pixel regions. These trenches extend deeply into the substrate, creating physical and electrical separation between adjacent pixels, thereby preventing crosstalk while maintaining small pixel dimensions for high resolution.
Solution Approach 2:
The patent transitions from two-dimensional surface isolation to three-dimensional deep trench isolation by extending isolation structures vertically deep into the substrate. This dimensional approach provides effective electrical isolation even when horizontal pixel spacing is minimized for high-resolution designs.
3Reliability
If metal isolation features with negative bias are implemented, then electrical isolation and quantum efficiency are improved, but device complexity increases
Solution Approach 1:
The metal isolation features perform multiple functions simultaneously: they act as electrical isolation barriers between pixels, serve as light reflectors to improve quantum efficiency, and provide mechanical support structures. This multi-functionality reduces the need for separate components, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent combines the isolation function and light reflection function into a single metal isolation feature structure. By merging these functions, the design avoids adding separate isolation layers and reflector structures, thus improving quantum efficiency and electrical isolation without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution boosts quantum efficiency and reduces crosstalk, enabling robust performance even in smaller image sensors by using metal isolation features and a negative bias to enhance electrical isolation.
Implementation Method 1
metal isolation features or metal deep trench isolation features that extend partially or completely through the semiconductor layer... serve as reflectors to further improve quantum efficiency
Implementation Method 2
A negative bias may be applied to the plurality of metal isolation features to improve electrical isolation
Data Source
AI summary
Image sensors and methods for forming the same are provided. A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.