Image Sensor Pixel Circuit Timing for Wide Dynamic Range
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Solution Overview
Problem
Existing solid-state imaging devices face challenges in achieving a wide dynamic range, high image capturing rates, and low noise performance, particularly in varying light conditions.
Innovation Solution
The implementation of a pixel circuit with a charge storage structure and amplification transistor, where the potential at the storage node controls the amplification transistor, and an amplifier drain circuit that transitions from a low potential to a high potential only after the reset period and before the readout period, enhancing the dynamic range without increasing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the amplifier drain circuit transitions from low potential to high potential early, then the dynamic range increases, but noise performance deteriorates
Solution Approach 1:
The amplifier drain circuit transitions to high potential in advance during the reset period, before the actual readout begins. This preliminary action allows the pixel capacitance to fully charge and stabilize, ensuring maximum dynamic range is achieved while the timing prevents noise interference during the critical readout phase
2Measurement precision
If the pixel capacitance is increased to expand dynamic range, then the light sensitivity range improves, but the image capturing speed decreases
Solution Approach 1:
The system employs periodic switching of the amplifier drain potential between low and high states, synchronized with the exposure and readout cycles. This periodic action allows the pixel capacitance to be fully utilized during exposure while enabling rapid reset and readout phases, thereby maintaining both wide dynamic range and high frame rates
Solution Approach 2:
The amplifier drain potential is dynamically changed between low and high levels at specific timing points. By changing this electrical parameter at the optimal moment (during reset period), the system maximizes the charge storage capability of the pixel capacitance without extending the exposure time, thus maintaining high image capturing speed
3Measurement precision
If the transition from low potential to high potential occurs before reset period ends, then the dynamic range increases, but the noise performance deteriorates
Solution Approach 1:
The potential transition is performed as a preliminary action during the reset period, allowing all charging processes to complete before readout begins. This timing ensures that the full dynamic range benefit is achieved while the noise from switching occurs outside the critical measurement window
Solution Approach 2:
The amplifier drain circuit rapidly transitions from low to high potential during the reset period, completing the charging process quickly and moving to the stable high state before readout. This rushing through of the transition phase minimizes the time during which noise could be generated while still achieving the full dynamic range effect
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the dynamic range and maintains high noise performance, facilitating fast image capturing across varying light conditions.
Implementation Method 1
photoelectric conversion elements generating a photocurrent with a current rating in proportion to the received radiation intensity
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
An image sensor assembly (10) includes a pixel circuit (100) including a charge storage structure (106) and an amplification transistor (110). A load path of the amplification transistor (110) is between an amplifier drain line (AMP D) and a pixel output node (PON). A potential at a storage node (FD) of the charge storage structure (106) controls the amplification transistor (110). An amplifier drain circuit (120) is configured to pass a low potential to the amplifier drain line (AMP_D) in a reset period and a high potential in a readout period. A transition from the low potential to the high potential is not before an end of the reset period and prior to a start of the readout period.