Image Sensor Pixel Transistor Vertical Layout for High Density
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Solution Overview
Problem
Current image sensors face challenges in maximizing the fill factor of photoelectric conversion elements while maintaining the area and characteristics of pixel transistors, especially when reducing the physical size of unit pixels to increase pixel density, which degrades their performance.
Innovation Solution
The image sensor design includes a pixel array with a substrate having a monocrystalline state, featuring a recess pattern and multiple gates strategically positioned to enhance carrier mobility and fill factor, with active regions extended in diagonal directions to accommodate pixel transistors efficiently, and a read-out circuit comprising transfer, reset, drive, and selection transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the physical size of unit pixels is reduced to increase pixel density, then the pixel density increases, but the performance of pixel transistors deteriorates
Solution Approach 1:
The patent transitions from planar transistor layout to a vertical three-dimensional structure by forming pixel transistors that extend in the depth direction beneath the photoelectric conversion element. This allows the transistor channel to occupy the vertical space rather than competing for horizontal area, enabling high pixel density while maintaining adequate transistor dimensions for proper performance
Solution Approach 2:
The patent implements a nested arrangement where the pixel transistor structure is positioned within and beneath the photoelectric conversion element volume. The transfer transistor, reset transistor, and other pixel circuit components are vertically integrated below the photodiode, allowing compact packaging while preserving transistor functionality
2Area of moving object
If the area of photoelectric conversion elements is maximized to improve fill factor, then the fill factor increases, but the area available for pixel transistors decreases
Solution Approach 1:
The patent resolves the area conflict by moving pixel transistor components from the horizontal plane to the vertical dimension. The photoelectric conversion element occupies the full horizontal area at the top layer, while transfer transistors, reset transistors, and other circuit elements are positioned in the vertical space beneath, allowing both components to achieve optimal area utilization
Solution Approach 2:
The patent segments the unit pixel into distinct vertical layers: the photoelectric conversion element occupies the upper horizontal space for light sensing, while the lower vertical space houses segmented transistor components (transfer transistor, reset transistor, drive transistor) that are spatially separated and functionally organized
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves carrier mobility and transfer efficiency, maintains high fill factor, and enhances the operational characteristics of pixel transistors, enabling high-speed operation and improved image signal generation despite reduced unit pixel size.
Implementation Method 1
a photoelectric conversion element
Data Source
AI summary
An image sensor includes: a pixel array including a plurality of unit pixels that are arrayed in two dimensions, wherein each of the plurality of the unit pixels includes: a substrate that including a photoelectric conversion element; a recess pattern formed in the substrate to overlap with the photoelectric conversion element and correspond to a center of the photoelectric conversion element; a first gate suitable for filling at least the recess pattern; a second gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a first diagonal direction; and a third gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a second diagonal direction which intersects with the first diagonal direction.