Image Sensor Port Segmentation for FPGA Pin Reduction
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Solution Overview
Problem
High-speed cameras with single, high-end FPGAs face challenges in efficiently processing and storing image data due to the high cost and limited bandwidth of their large number of pins, which restricts the ability to increase memory bandwidth.
Innovation Solution
The camera architecture employs multiple FPGAs or ASICs connected to subsets of image sensor ports, with each processing device performing image data pre-processing and writing directly to separate memory blocks, reducing the number of pins required and allowing for wider memory interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single high-end FPGA is used to process all image sensor ports, then processing capability is improved, but cost and pin bandwidth are excessively high
Solution Approach 1:
The patent divides the image sensor ports into multiple groups, with each group connected to a separate processing device (FPGA or ASIC). This segmentation allows the system to handle the same total data volume using multiple lower-cost, lower-pin-count devices instead of one high-end device, directly resolving the contradiction between processing capability and device complexity/cost.
2Quantity of substance
If all image sensor data is written to a single memory block, then memory capacity is sufficient, but memory bandwidth is limited
Solution Approach 1:
The patent divides the memory system into multiple memory blocks, with each processing device writing to its own dedicated memory block. This parallel memory architecture enables multiple simultaneous write operations, significantly increasing total memory bandwidth while maintaining sufficient total capacity for high-speed applications.
3Device complexity
If a single processing device handles all data, then device count is low, but memory interface width is restricted
Solution Approach 1:
The patent assigns dedicated memory interfaces to each processing device, allowing each to operate at full speed independently. This results in a total system interface width that is the sum of all individual interfaces, enabling much wider effective bandwidth compared to a single shared interface.
Data Source
AI summary
A camera includes a first processing device, a second processing device, and an image sensor that has a first plurality of ports connected to the first processing device and a second plurality of ports connected to the second processing device. A method includes providing first data from the first plurality of ports of the image sensor to the first processing device, and providing second data from the second plurality of ports of the image sensor to the second processing device. Another camera includes a first memory, a second memory, and an image sensor having a first plurality of ports connected to the first memory and a second plurality of ports connected to the second memory. A method includes providing first data from the first plurality of ports to the first memory and providing second data from the second plurality of ports to the second memory.