Image Sensor Wiring Layout for Pre-CSP Prototype Evaluation
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Solution Overview
Problem
Imaging devices with WLCSP structure face challenges in reducing the time required for prototype evaluation, as existing methods often require going through the CSP process, leading to longer development and analysis periods, which affects competitiveness and increases chip size and costs.
Innovation Solution
Incorporating an extended wiring section in the peripheral area of the imaging device, allowing for prototype evaluation before the CSP process by coupling a test pad electrode to one end of the extended wiring section, which is electrically coupled to the multilayer wiring layer, enabling signal input and output from the light incident surface side.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CSP process is completed before prototype evaluation, then the imaging device can be properly packaged and protected, but the evaluation time is significantly extended
Solution Approach 1:
The extended wiring section is constructed in advance during the semiconductor substrate manufacturing process, before the CSP packaging is completed. This preliminary preparation allows the wiring path to be ready for immediate use once the light receiving element is mounted, eliminating the need to wait for CSP completion before performing electrical evaluations.
Solution Approach 2:
The extended wiring section acts as an intermediary connection that bridges the light receiving element and the external evaluation environment. By extending the wiring to the peripheral area and making it accessible from the light incident surface side, it provides a mediation path for electrical signals without requiring the complete CSP packaging to be finished first.
2Loss of time
If the extended wiring section is provided in the peripheral area, then prototype evaluation can be performed earlier, but the chip area increases
Solution Approach 1:
The extended wiring section is localized to the peripheral area of the semiconductor substrate, which is a region that would otherwise be unused or minimally utilized. By concentrating the evaluation functionality in this specific local area rather than distributing it across the entire chip, the patent minimizes the impact on the overall active imaging area while still providing the necessary evaluation capabilities.
3Ease of operation
If the extended wiring section is made accessible from the light incident surface side, then evaluation becomes easier and faster, but the wiring layer complexity increases
Solution Approach 1:
The patent extends the wiring from the traditional back-side access (through the CSP package) to the front-side access (light incident surface side) by utilizing the peripheral area in a different spatial dimension. This dimensional repositioning allows evaluation probes to access the wiring from the front surface, simplifying the evaluation process while the multilayer wiring structure manages the internal complexity.
Data Source
AI summary
An imaging device including: pixel area and a peripheral area that lies outside the pixel area; light receiving element provided in the pixel area; circuit board provided in the pixel area and the peripheral area, the circuit board including a semiconductor substrate and a multilayer wiring layer, the multilayer wiring layer being provided between the semiconductor substrate and the light receiving element; first wiring line provided in the multilayer wiring layer, the first wiring line being electrically coupled to the light receiving element; a protective member that is opposed to the circuit board, the protective member and the circuit board sandwiching the light receiving element; and an extended wiring section provided between the semiconductor substrate and the protective member in the peripheral area, one end of the extended wiring section being open and another end of the extended wiring section being electrically coupled to the first wiring line.