Image Sensor Pulse Generator for Low-Power High-Speed ADCs
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Solution Overview
Problem
As the number of pixels in image sensors increases, the high-speed operation of analog-to-digital converters (ADCs) leads to increased power consumption due to higher counter frequencies, which is not efficiently managed by existing technologies.
Innovation Solution
The proposed solution involves an image sensor design that includes a counting code generator, a correlated double sampling circuit, a pulse generator synchronized with a clock signal, and a counter circuit, which together reduce power consumption by generating a pulse signal with consistent width, independent of power changes, and optimizing the pulse generator's operation to align with clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the ADC operates at high speed to handle increased pixel numbers, then productivity is improved, but power consumption increases due to higher counter frequencies
Solution Approach 1:
The pulse generator produces periodic pulse signals synchronized with the clock signal, enabling the counter to operate in a rhythmic manner. This periodic action allows the system to maintain high conversion speed while controlling power consumption by confining active counting operations to specific clock cycles rather than continuous high-frequency operation.
Solution Approach 2:
The system dynamically adjusts the operating parameters by synchronizing the pulse generator with the clock signal and using the comparison signal to control when counting occurs. This parameter change approach allows the ADC to adapt its operation mode, achieving high speed when needed while reducing power consumption during stable states.
2Productivity
If the counter frequency increases to match high-speed ADC operation, then productivity is improved, but power consumption increases proportionally
Solution Approach 1:
The comparison circuit provides feedback by generating a comparison signal based on the relationship between the pixel signal and ramp signal. This feedback mechanism controls the pulse generator to produce pulses only when needed, allowing the counter to operate at high frequency selectively rather than continuously, thus improving conversion rate while managing power consumption.
Solution Approach 2:
The counter operates periodically based on the clock signal and comparison signal rather than continuously. This periodic operation allows the counter to achieve high conversion rates during active periods while consuming less power during inactive periods, resolving the contradiction between productivity and power consumption.
Data Source
AI summary
An image sensor is provided. The image sensor includes a counting code generator configured to generate a counting code, a pixel array including at least one pixel, a correlated double sampling (CDS) circuit configured to compare a magnitude of a pixel signal output from the at least one pixel with a magnitude of a ramp signal and to output a corresponding comparison signal, a pulse generator configured to generate a pulse signal synchronized with a first clock signal based on the comparison signal, and a counter circuit configured to latch a value of the counting code to correspond to a transition of a level of the comparison signal based on the pulse signal.