Image Sensor Readout Circuitry for Parallel Pixel Binning
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Solution Overview
Problem
Continuous time analogue to digital converter architectures in image sensors are not well suited for analogue binning, which limits the improvement of frame rate when averaging data from multiple pixels, as they require sequential access and multiple conversions, thereby not enhancing the signal-to-noise ratio or frame rate effectively.
Innovation Solution
The implementation of a pixel array circuitry with multiple column bitlines and a readout input circuit connected via separate capacitances to a comparator input node, allowing for concurrent reading and averaging of data from multiple pixels using a continuous time analogue to digital converter architecture, which doubles the frame rate by enabling simultaneous data acquisition from multiple rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a continuous time analogue to digital converter architecture is used, then the conversion speed is improved, but the suitability for analogue binning deteriorates
Solution Approach 1:
The pixel array is divided into multiple banks, with each bank having its own independent continuous time ADC. This segmentation allows each ADC to handle a subset of pixels simultaneously, enabling analogue binning operations across multiple pixels without requiring sequential access, thus maintaining both high conversion speed and suitability for analogue binning
Solution Approach 2:
The readout circuitry is designed to support multiple operating modes including full-resolution readout, analogue binning, and different binning configurations (2x2, 2x4, etc.). The same hardware infrastructure can adapt to different modes by reconfiguring the connection between pixel banks and ADCs, providing universal functionality that satisfies both speed requirements and analogue binning capability
2Device complexity
If sequential access to pixels is used, then the device complexity is reduced, but the frame rate deteriorates
Solution Approach 1:
The pixel array is divided into multiple banks that can be read out in parallel by multiple ADCs. This segmentation enables simultaneous data acquisition from multiple rows or columns, doubling or quadrupling the effective frame rate depending on the number of banks and ADCs, while each individual ADC maintains relatively simple circuitry
Solution Approach 2:
The patent introduces a bank dimension in addition to the traditional row and column dimensions. By organizing pixels into banks that can be independently accessed and by providing multiple ADCs that can operate simultaneously on different banks, the system adds a temporal parallelism dimension that increases frame rate without proportionally increasing the complexity of individual readout circuits
3Productivity
If multiple ADCs are used to read out multiple pixel banks in parallel, then the throughput is improved, but the device complexity increases
Solution Approach 1:
Multiple ADCs are merged into a unified readout architecture that shares common control logic and timing mechanisms. The pixel banks are grouped and assigned to ADCs in a systematic manner, allowing parallel operation while reducing overall complexity through resource sharing and standardized interfaces between banks and converters
Solution Approach 2:
The readout circuitry is designed with universal components that can function in multiple configurations. The same ADC circuitry can handle different pixel bank assignments, and the control logic can adapt to different operating modes (full resolution, binning modes), reducing the need for dedicated complex circuitry for each specific function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively doubles the frame rate by allowing concurrent data readout from multiple rows, improving throughput and signal-to-noise ratio through analogue binning, while maintaining full resolution capabilities by adjusting capacitor ratios and switch matrix configurations.
Implementation Method 1
each of said first inputs and said second input being connected via a separate capacitance in parallel to each other to a single comparator input node; said readout input circuit being further operable such that said analogue signals at said first inputs and a reference signal from a time varying reference circuit on said second input are constantly read onto their respective capacitances during both the first calibration period and the second read period
Implementation Method 2
said readout comparator circuit is operable to compare an average of the signals on each of said plurality of first inputs to said reference signal
Data Source
Figure 1~2
Figure 3
Figure 4a~4b
AI summary
Disclosed is an image sensor comprising: a plurality of pixels arranged in rows and columns to form a pixel array, each pixel column comprising at least two column bitlines, such that an output of each pixel is connected to one of the column bitlines of the column of which it is comprised; a readout input circuit comprising a plurality of first inputs and a second input, each of the first inputs and the second input being connected via a capacitance to a single comparator input node; and a readout comparator circuit connected to the single comparator input node. Each of the first inputs receives, in parallel, an analogue signal, the analogue signals being acquired from the signal output of one or more of the pixels via the column bitline to which the pixel is connected, the analogue signals varying during a pixel readout period and having a first level during a first calibration period and a second level during a second read period. The analogue signals at the first inputs and a reference signal from a time varying reference circuit on the second input are constantly read onto their respective capacitances during both the first calibration period and the second read period. The readout comparator circuit compares an average of the signals on each of the plurality of first inputs to the reference signal.