Image Sensor Row Driver Time Delay Circuit Power Surge Mitigation
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Solution Overview
Problem
Global events in image sensor pixel arrays, such as global reset and charge transfer operations, cause large current/power surges in supply and grounding lines, leading to performance variations and increased complexity in power delivery networks.
Innovation Solution
Incorporating time delay circuits in row driver circuitry to stagger the timing of global control signals, thereby reducing peak current draw by distributing the global events across different pixel rows at slightly different times, using programmable delays to ensure uniform distribution and minimize power surges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If global events (reset, charge transfer) are executed simultaneously across all pixel rows, then integration time synchronization is maintained, but large current/power surges occur in shared supply and grounding lines
Solution Approach 1:
The patent divides the simultaneous global event execution across all pixel rows into segmented, staggered events. Each pixel row executes its global event (reset or charge transfer) at a different time offset, spreading the current draw across multiple time slots rather than concentrating it simultaneously. This segmentation of the global event execution timeline resolves the contradiction by maintaining integration time synchronization through programmed offsets while reducing peak current surges in shared power lines.
2Reliability
If more complex power delivery networks are used to mitigate current surges, then pixel performance consistency is improved, but device complexity increases
Solution Approach 1:
The patent changes the timing parameter of global event execution for each pixel row, introducing programmed time offsets in the control signals. By modifying the temporal parameter (execution time) rather than the power delivery network structure, the patent achieves pixel performance consistency by reducing current surges without increasing device complexity. This parameter change approach resolves the contradiction by achieving performance uniformity through timing adjustment rather than through complex power network design.
3Power
If global events are staggered across different pixel rows, then peak current draw is reduced, but integration time synchronization may be affected
Solution Approach 1:
The patent applies preliminary action by pre-programming time offsets into the control signals for each pixel row before the global events are executed. These predetermined offsets are calculated to ensure that despite the staggered execution timing, all pixel rows complete their integration periods synchronously. This preliminary configuration of timing parameters resolves the contradiction by ensuring integration time synchronization is maintained even as global events are staggered to reduce peak current draw.
Data Source
AI summary
An image sensor may include a pixel array, row control circuitry, and column readout circuitry. The row control circuitry may operate the pixel array in a global shutter mode of operation. In particular, timing control circuitry may provide global timing clock signals associated with a global photodiode reset event and a global photodiode charge transfer event to row driver circuitry providing control signals to each row in the array. Each driver circuitry may include a time delay circuit that delays the global timing clock signal by different amounts across the rows. Therefore, these global events may be offset on a per-row or per-row group basis, thereby mitigating power surges associated with global events. Further, by offsetting the global photodiode reset and charge transfer events using the same delay for a given row, the same global integration time may be preserved across different rows.