Solid-State Image Sensor SAR ADC Readout for Multi-Row Speed
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Solution Overview
Problem
Conventional solid-state imaging elements face challenges in improving reading speed while maintaining image quality and controlling circuit scale, as they require sequential row-by-row signal processing and AD conversion, which limits the quantifying bit number and increases circuit complexity.
Innovation Solution
The implementation of successive approximation analog-to-digital converters (SARADCs) that drive multiple rows of pixels simultaneously, allowing for parallel AD conversion and reduced settling time, coupled with a comparator that varies a reference signal to generate pixel signals efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If single-slope ADCs are arranged in columns to perform AD conversion row by row, then the reading speed can be improved by reducing quantifying bit number, but the image quality of image data is reduced
Solution Approach 1:
The patent changes the conversion method from single-slope ADC to successive approximation ADC, which fundamentally alters the conversion mechanism. This parameter change enables high-speed conversion without compromising precision, as successive approximation ADC achieves linear conversion characteristics and high accuracy through its binary search algorithm, unlike single-slope ADC which requires long conversion times
Solution Approach 2:
The patent introduces dynamic row selection capability where the row selection section can selectively select any row based on imaging conditions. This dynamic adaptation allows the system to optimize between reading speed and image quality by adjusting which rows are converted and when, rather than being locked into sequential row-by-row processing
2Speed
If two ADCs are provided for each column to drive two rows at the same time, then the reading speed can be doubled, but the number of ADCs increases
Solution Approach 1:
The patent segments the pixel array into multiple blocks along the row direction, with each block independently selectable by the row selection section. This segmentation allows parallel processing of different row blocks without requiring duplicate ADC circuits, as a single successive approximation ADC can sequentially or concurrently serve multiple segmented blocks through rapid switching
Solution Approach 2:
The successive approximation ADC is designed with multi-functionality to handle multiple row blocks and different conversion modes. The same ADC circuit can convert signals from different rows by switching the input source, eliminating the need for dedicated ADCs for each row while maintaining high reading speed through efficient time-multiplexed operation
3Measurement precision
If sequential row-by-row driving is performed with constant settling time, then the AD conversion can be completed accurately, but the reading time increases
Solution Approach 1:
The patent implements periodic row selection and conversion cycles where the row selection section systematically selects different rows in a repeating pattern. This periodic action allows the system to maintain accurate conversion by ensuring each row receives adequate settling time while improving overall reading speed by keeping the ADC continuously busy through structured repetition of conversion cycles across multiple rows
Solution Approach 2:
The row selection is performed in advance before AD conversion begins, with the row selection section pre-selecting which rows will be converted in upcoming cycles. This preliminary selection allows the system to optimize conversion timing and ensure proper settling time allocation for each row before conversion starts, preventing time conflicts between settling and conversion operations
Data Source
AI summary
It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC.A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.