Solid-State Image Sensor A/D Coding for Clock Skew Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In solid-state imaging apparatuses, significant clock signal skew leads to large errors in A/D conversion accuracy, degrading the resolution without increasing clock signal frequency.
Innovation Solution
The implementation of a counter code comprising low-order bit codes with phase-shifted clock signals and high-order bit codes using gray codes, where the count value changes only the logical level of a 1-bit signal, minimizing errors even with significant clock signal skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple clock signals with different phases are used for low-order bit code, then resolution is improved, but clock signal skew causes large errors that degrade A/D conversion accuracy
Solution Approach 1:
The counter code is segmented into two distinct parts: low-order bit code generated by multiple phase-shifted clock signals, and high-order bit code generated by a gray code counter. This segmentation allows each part to serve its specific function while minimizing the negative effects of clock skew on overall conversion accuracy.
Solution Approach 2:
The patent creates a composite counter code structure combining binary-coded low-order bits with gray-coded high-order bits. This composite approach leverages the advantages of both coding schemes: the fine resolution of binary coding for low-order bits and the skew-immunity of gray coding for high-order bits, achieving high accuracy without requiring extremely high clock frequencies.
2Measurement precision
If clock signal frequency is increased to improve resolution, then A/D conversion precision is improved, but clock signal skew increases causing larger errors
Solution Approach 1:
The patent changes the coding parameter from pure binary to gray code for the high-order bits, fundamentally altering how count values are represented. This parameter change makes the system immune to clock skew effects while maintaining the ability to achieve high resolution through the combined low-order and high-order bit codes, without needing to increase clock frequency.
3Productivity
If binary code is used for high-order bit code, then count value varies synchronously with clock signal, but clock skew causes large errors in A/D conversion
Solution Approach 1:
The patent creates a composite counter code structure combining binary-coded low-order bits with gray-coded high-order bits. This composite approach leverages the advantages of both coding schemes: the fine resolution of binary coding for low-order bits and the skew-immunity of gray coding for high-order bits, achieving high accuracy without requiring extremely high clock frequencies.
Data Source
AI summary
There is a need to provide a solid-state imaging apparatus capable of highly accurately analog-to-digital converting an analog voltage output from a pixel circuit. The solid-state imaging apparatus supplies a counter code to an integral A/D converter. The counter code CD includes 3-phase clock signals and gray signals. The clock signals each have a cycle equal to specified cycle multiplied by 8 and allow phases to shift from each other by specified cycle. The gray signals linearly increase count values at a cycle equal to specified cycle multiplied by 4. The counter code reverses only the logical level of a signal when a count value changes. A count value error can be limited to a minimum.