CMOS Image Sensor SRAM Power Gating for Global Shutter ADC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS image sensors with column-parallel ADCs face challenges in achieving global shutter functionality and high frame rates due to shoot-through currents during SRAM writing, leading to limited dynamic range and increased noise.
Innovation Solution
The implementation of a solid-state imaging device with a pixel structure that includes a photoelectric conversion element, a transfer element, an output buffer, a comparator for AD conversion, and a static random access memory (SRAM) with power gating transistors to control current flow, effectively blocking shoot-through currents and optimizing writing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SRAM is used for ADC code storage in each pixel, then the global shutter function and high frame rate are enabled, but shoot-through currents occur during writing operations causing limited dynamic range and increased noise
Solution Approach 1:
A power gating transistor is introduced as an intermediary element between the power supply and the SRAM bit cell. This transistor acts as a mediator that selectively controls power delivery to the SRAM, enabling writing operations while preventing harmful shoot-through currents from occurring during the writing process, thus resolving the contradiction between high-speed operation and current suppression.
2Area of stationary object
If SRAM bit cells are used for ADC memory, then the pixel pitch can be reduced and image quality improved, but the writing operation becomes complex due to simultaneous writing in all pixels
Solution Approach 1:
The writing operation to SRAM bit cells is performed in a periodic manner synchronized with the pixel reading operation. By timing the writing operation to occur during specific periods when pixels are being read out, the system achieves simultaneous writing to all SRAM bit cells without requiring complex control circuitry, thus reducing pixel pitch while maintaining manageable operational complexity.
3Productivity
If conventional CMOS image sensor reading operation is used, then column parallel output processing is achieved, but global shutter functionality cannot be implemented
Solution Approach 1:
The image sensor is segmented into multiple independent pixel units, each containing its own SRAM bit cell for ADC code storage. This segmentation allows each pixel to operate independently with its own memory element, enabling the global shutter function where all pixels can capture and store image data simultaneously, while maintaining the high-speed column parallel output processing capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient writing operations, widening the dynamic range, enhancing frame rates, reducing noise, and maximizing the effective pixel region while maintaining cost-effectiveness.
Implementation Method 1
a first first-conductivity-type transistor connected between a power supply and a virtual power supply node... blocking the shoot-through currents from the bit cells
Implementation Method 2
a photodiode (a photoelectric conversion element) and a floating diffusion (FD) amplifier... photoelectric conversion element for detecting light and generating charges
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Provided are a solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus. A memory part 230 is formed using an SRAM 231 serving as an ADC memory, and an ADC code is written into and read from the memory part 230 under control of a reading part 60. In the SRAM 231, a power gating transistor is additionally provided to both of a power supply node (between a power supply and a virtual power supply node) and a ground node (between a virtual reference potential node and a reference potential) for the purposes of blocking the shoot-through currents from the bit cells during the writing operation. The power gating transistors are controlled by the reading part 60 so as to operate as either a weak current source or switch.