3D Stacked Image Sensor Pixel Layout for Noise and Conversion Efficiency
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Solution Overview
Problem
The decreasing size of pixels in image sensors due to increasing integration leads to issues such as increased noise and decreased photoelectric conversion efficiency.
Innovation Solution
The image sensor design includes a stacked structure with a first stack containing a photoelectric conversion region and a floating diffusion region, a second stack with a pixel gate electrically connected to the floating diffusion region, and a third stack with a logic transistor providing signals to the pixel gate and transmission gate. This configuration allows for improved signal transmission and reduced noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel size is reduced to increase integration degree, then integration density is improved, but noise increases and photoelectric conversion efficiency decreases
Solution Approach 1:
The patent transitions from a planar pixel structure to a three-dimensional stacked structure with multiple layers. The pixel circuit components are vertically arranged in stacks above the photoelectric conversion region, utilizing the vertical dimension to increase integration density while preserving the horizontal photoelectric conversion area, thereby maintaining efficiency while reducing noise through improved component isolation.
Solution Approach 2:
The pixel structure is segmented into distinct functional stacks: a photoelectric conversion stack, a first pixel circuit stack, and a second pixel circuit stack. This segmentation isolates noise-generating components from the photoelectric conversion region, allowing each stack to be optimized independently while maintaining overall pixel performance despite reduced size.
2Productivity
If pixel size is reduced to increase integration degree, then integration density is improved, but photoelectric conversion efficiency decreases
Solution Approach 1:
By moving pixel circuit components to vertical stacks above the photoelectric conversion region, the invention preserves the horizontal photoelectric conversion area even as overall pixel size decreases. This dimensional transition allows the photoelectric conversion region to maintain its efficiency while accommodating more circuit elements in the vertical space.
Solution Approach 2:
The patent introduces intermediate structures such as insulating layers and etch stop films between the photoelectric conversion region and the pixel circuit stacks. These intermediary layers provide electrical isolation and mechanical support, ensuring that the photoelectric conversion efficiency is not compromised by the presence of overlying circuit components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves excellent image quality even with small pixel sizes by reducing noise and maintaining high photoelectric conversion efficiency, thereby addressing the challenges posed by decreasing pixel sizes.
Implementation Method 1
a photoelectric conversion region in the first semiconductor substrate
Data Source
AI summary
An image sensor is described comprising a first, a second, and a third stack mounted together. The first stack includes a first semiconductor substrate with a photoelectric conversion region, a floating diffusion region, and a transmission gate. The photoelectric conversion region absorbs light, and the charges freed by the light absorption are stored in the floating diffusion region prior to being transferred to other circuitry by the transmission gate. The transmission gate comprises an etch stop film on an upper surface and on a sidewall. The second stack, attached to the first stack, includes a second semiconductor substrate in which is located a pixel gate. The pixel gate is electrically connected with the floating diffusion region and further comprises a gate spacer on a sidewall of the pixel gate. The third stack, attached to the second stack, includes a logic transistor.