Backside-Illuminated Image Sensor Stacking for Lower-Cost Yield
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Solution Overview
Problem
Existing technologies for manufacturing solid-state image pickup apparatuses face challenges in reducing manufacturing costs due to issues with chip size mismatch, yield reduction, and increased power consumption.
Innovation Solution
A backside-illumination solid-state image pickup apparatus is designed with a first semiconductor element having an image pickup element, and smaller second and third semiconductor elements with embedded signal processing circuits, connected by a communication wire. This configuration allows for efficient signal processing and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the number of connection terminals is increased to divide transfer and reduce signal rate, then power consumption is reduced, but the package size of each circuit becomes larger
Solution Approach 1:
The patent transitions from a planar arrangement of circuits to a three-dimensional stacked configuration. Multiple circuit packages are vertically stacked and interconnected through through-silicon vias (TSVs), enabling signal distribution across multiple layers. This vertical integration allows increased connection terminals without proportionally increasing the footprint area, as connections are distributed across the stack height rather than spread out in a single plane.
2Area of stationary object
If WoW stacking technology is used to reduce configuration size, then package size is reduced, but manufacturing cost increases due to chip size mismatch and yield reduction
Solution Approach 1:
The patent segments the semiconductor wafer into multiple independent circuit packages during the manufacturing process. Each package contains its own circuits and is sized according to its specific requirements rather than being constrained by the largest chip on the wafer. This segmentation allows optimal utilization of wafer area, improving theoretical yield while maintaining compact stacked configuration. The segmentation is achieved through strategic dicing patterns that create packages of varying sizes suitable for different circuit functions.
Solution Approach 2:
The patent changes the manufacturing parameters by allowing different package sizes within the same wafer stack. Instead of requiring all chips to be uniform in size as in traditional WoW, the system accommodates variable package dimensions optimized for specific circuit requirements. This parameter flexibility improves wafer utilization and reduces manufacturing costs while maintaining the space-saving stacked configuration.
3Productivity
If small-sized bumps are used to connect chips with different sizes, then yield is improved, but connection pitch is limited and manufacturing complexity increases
Solution Approach 1:
The patent extracts the connection function from surface-mounted bumps to vertically penetrating through-silicon vias (TSVs). Instead of using small bumps that require precise placement and limit connection pitch, TSVs provide direct vertical connections through the substrate. This extraction of the connection mechanism eliminates pitch limitations and reduces manufacturing complexity by using standard semiconductor fabrication processes for via formation rather than requiring精密 bump alignment.
Data Source
AI summary
A backside-illumination solid-state image pickup apparatus and a backside-illumination solid-state image-pickup-apparatus manufacturing method, an image pickup apparatus, and electronic equipment that are configured to make it possible to reduce manufacturing costs. A diced memory circuit and logic circuit are laid out in a horizontal direction, are embedded and flattened by using an oxide film, and are stacked so as to be enclosed in a plane direction under a solid-state image pickup element. The present disclosure can be applied to an image pickup apparatus.