Image Sensor Peripheral Transistors With Strain-Engineered Channels
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Solution Overview
Problem
Current imaging devices face challenges in optimizing the performance of peripheral transistors relative to pixel transistors, particularly in terms of strain introduction and impurity distribution, which affects carrier mobility and noise suppression.
Innovation Solution
The imaging device incorporates a peripheral region with transistors featuring a strain-introducing layer, such as a silicon germanium or carbon nanotube layer, and specific impurity profiles to enhance carrier mobility and suppress transient enhanced diffusion, while maintaining a thinner gate insulator film and shallow trench isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a strain-introducing layer is added to peripheral transistors to improve carrier mobility, then the performance of peripheral transistors is enhanced, but the device structure becomes more complex
Solution Approach 1:
The strain-introducing layer is selectively applied only to peripheral transistors that require enhanced carrier mobility, while pixel transistors maintain their original structure. This localized application optimizes performance where needed without unnecessarily complicating the entire device structure.
Solution Approach 2:
The patent employs composite material structures by integrating strain-introducing layers (such as silicon germanium or cubic silicon carbide) with the semiconductor substrate. These composite structures provide both mechanical strain for improved carrier mobility and electrical isolation functions.
2Speed
If the gate insulator film is made thinner to improve transistor performance, then switching speed increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent systematically varies gate insulator thickness parameters across different transistor types. Peripheral transistors utilize thinner gate insulators (5-15 nm) for high-speed switching, while pixel transistors employ thicker gate insulators (15-30 nm) for stability, optimizing each region's performance characteristics.
3Reliability
If impurity concentration is increased in peripheral transistors to improve conductivity, then electrical performance improves, but transient enhanced diffusion increases causing quality degradation
Solution Approach 1:
The patent implements preliminary impurity distribution planning by configuring specific impurity profiles before transistor fabrication. Low-concentration impurity regions are prepared in advance to prevent transient enhanced diffusion, while high-concentration regions are strategically placed where conductivity is needed but diffusion risks are minimized.
Solution Approach 2:
Different impurity concentration levels are applied to different regions of the peripheral transistors. High-concentration impurity regions provide necessary conductivity, while low-concentration regions prevent transient enhanced diffusion, creating a spatially optimized impurity distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance of the imaging device by increasing carrier mobility, reducing noise, and maintaining a compact transistor size, thereby enhancing image quality and reducing manufacturing complexities.
Implementation Method 1
a first strain-introducing layer that brings a strain to the first channel region
Data Source
AI summary
An imaging device includes a pixel region and a first peripheral region. The pixel region includes a pixel substrate portion and a pixel transistor located in the pixel substrate portion. The first peripheral region includes a first peripheral substrate portion and at least one first peripheral transistor located in the first peripheral substrate portion. Signals are transmitted between the first peripheral region and the pixel region. A gate length of the at least one first peripheral transistor is less than a gate length of the pixel transistor. The at least one first peripheral transistor further includes, in the first peripheral substrate portion, a first source, a first drain, a first channel region located between the first source and the first drain, and a first strain-introducing layer that brings a strain to the first channel region.