Image Sensor Supplemental Capacitive Coupling Node
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Solution Overview
Problem
CMOS image sensors face challenges in achieving high conversion gain for low-light sensitivity while maintaining full well capacity and avoiding pixel saturation in bright environments, as pixel sizes shrink and fill factor is reduced by adding supplemental capacitance and controlling transistors.
Innovation Solution
The implementation of a dual conversion gain feature through a supplemental capacitive coupling node, where a supplemental capacitor and control transistor are added to each pixel cell, allowing the capacitance of the floating diffusion node to be selectively increased or decreased based on light conditions, thereby adjusting the conversion gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the capacitance of the floating diffusion node is reduced to increase conversion gain, then low-light sensitivity is improved, but pixel saturation occurs in bright environments
Solution Approach 1:
The patent implements a switchable capacitor that can dynamically change its capacitance value based on lighting conditions. The capacitor is connected in parallel with the floating diffusion node capacitance and can be selectively activated or deactivated through a control transistor, allowing the total capacitance to be adjusted between a first value (higher capacitance for bright environments) and a second value (lower capacitance for low-light environments), thus resolving the contradiction between conversion gain and full well capacity
Solution Approach 2:
The patent changes the capacitance parameter of the floating diffusion node by using a switchable capacitor with different capacitance values. The control circuit adjusts the capacitance parameter based on the operating conditions (lighting environment), enabling the system to optimize conversion gain for low-light sensitivity while maintaining full well capacity for bright environment operation
2Productivity
If pixel cell sizes are reduced to meet higher resolution demands, then integration density is improved, but conversion gain decreases and low-light sensitivity worsens
Solution Approach 1:
The patent compensates for the decreased conversion gain caused by smaller pixel sizes by introducing a switchable capacitor that can provide additional capacitance when needed. This allows the floating diffusion node to maintain appropriate capacitance values for high conversion gain even in miniaturized pixel cells, thereby preserving low-light sensitivity while achieving higher integration density
3Adaptability or versatility
If supplemental capacitance is added to increase full well capacity, then pixel saturation is avoided, but conversion gain decreases and low-light sensitivity worsens
Solution Approach 1:
The patent uses a dynamic capacitor configuration where the supplemental capacitance can be selectively activated or deactivated. The control transistor allows the system to switch between a state with supplemental capacitance (for bright environments requiring high full well capacity) and a state without supplemental capacitance (for low-light environments requiring high conversion gain), thus resolving the contradiction between full well capacity and conversion gain
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances low-light sensitivity with reduced read noise while maintaining high full well capacity in high-light environments, improving the signal-to-noise ratio and reducing image lag by dynamically adjusting the conversion gain based on lighting conditions.
Implementation Method 1
The capacitance of the floating diffusion node can be selectively increased or decreased by coupling a supplemental capacitor to the floating diffusion node
Implementation Method 2
a photoelectric conversion unit, transfer switch and amplification transistor... As photogenerated electrons accumulate on the photodiode PD
Data Source
AI summary
An image sensor includes a pixel array, a bit line, supplemental capacitance node line, and a supplemental capacitance circuit. The pixel array includes a plurality of pixel cells each including a floating diffusion ("FD") node and a photosensitive element coupled to selectively transfer image charge to the FD node. The bit line is coupled to selectively conduct image data output from a first group of the pixel cells. The supplemental capacitance node line is coupled to the FD node of a second group of the pixel cells to selectively couple a supplemental capacitance to the FD nodes of the second group in response to a control signal. In various embodiments, the first and second group of pixel cells may be the same group or a different group of the pixel cells and may add a capacitive boost feature or a multi conversion gain feature.