Image Sensor Transfer Gate Negative Potential Control
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Solution Overview
Problem
Existing electronic image sensors with active pixels face issues of dark current due to interface defects between the photodiode and insulating silicon oxide, leading to reduced signal-to-noise ratio, especially under low illumination conditions, and current inrush difficulties when switching transfer gates.
Innovation Solution
The method involves bringing the transfer and reset gates to a negative potential during most of the charge integration time using a charge pump, with a controlled signal that transitions through zero potential to minimize current inrush, and using a specific pulse profile that includes phases from positive to zero to negative voltage to reduce capacitive discharge current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a P-type region is implanted to passivate interface defects and reduce dark current, then dark current is reduced, but it cannot be placed under transistor gates due to process constraints
Solution Approach 1:
The patent applies different potential conditions to different regions: the transfer gate is held at negative potential during integration to passivate interface defects locally under the gate, while other regions maintain their normal operation. This localized approach reduces dark current without requiring global process changes
Solution Approach 2:
The patent changes the electrical parameter (potential) of the transfer gate from the conventional positive or zero potential to a negative potential during the integration phase. This parameter change creates a depletion region that passivates interface defects, reducing dark current generation at the oxide-silicon interface
2Object-affected harmful factors
If the transfer gate is switched from positive to negative potential, then dark current is reduced, but a large current inrush occurs during switching
Solution Approach 1:
The patent employs periodic control of the transfer gate potential with distinct phases: a gradual transition phase from positive to negative potential, a stable negative phase during integration, and a controlled return phase. This periodic action with optimized timing reduces current inrush while maintaining dark current suppression
Solution Approach 2:
The patent applies a preliminary negative potential phase before the main transfer operation. This preliminary action prepares the interface by creating a depletion region that prevents dark current generation, and the timing is optimized to allow charge redistribution before full operation, reducing current inrush
3Object-affected harmful factors
If the transfer gate is held at negative potential during integration, then dark current is reduced, but power consumption increases due to charge pump operation
Solution Approach 1:
The charge pump operates periodically only during the brief transition phases rather than continuously. The negative potential is maintained during integration without continuous pumping, reducing power consumption while still achieving dark current suppression during the critical integration period
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces dark current and minimizes current inrush, improving the signal-to-noise ratio and efficiency by maintaining the negative potential with reduced power consumption.
Implementation Method 1
the transfer and reset gates are brought to a negative potential during most of the charge integration time using a charge pump
Implementation Method 2
each pixel comprising a photodiode formed in a semiconductor active layer... transferring the charges generated by the light from the photodiode
Data Source
Figure 1~2
Figure 3~5B
Figure 6
AI summary
The invention relates to a method of image capture in an image sensor with a matrix of rows and columns of active pixels, supplied between a first power supply terminal of zero potential (Vss) and a second power supply terminal at a positive supply potential (Vdd). Each pixel comprises a photodiode and a gate for transferring the photogenerated charges to a charge storage node. The transfer gate is brought by a charge pump to a negative potential (VNEG) for the duration of the charge integration and receives a transfer control signal (TRA) common to all the pixels during a transfer time window. The transfer or reinitialization control signal comprises in succession at least one first phase during which it passes from the negative potential (VNEG) to a positive transfer potential, a second phase during which it passes from the positive transfer potential to the zero potential provided by the first power supply terminal, a third phase of finite duration during which it remains at the zero potential, and a fourth phase in which it passes back from the zero potential to the negative potential provided by the charge pump. The fact of involving the power supply potential limits the inrushes of current into the charge pump which must re-establish the negative potential (VNEG) at the end of the transfer.