Image Sensor Transistor Parasitic Capacitor Integration
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Solution Overview
Problem
Conventional image sensors face challenges in increasing integration density while maintaining sufficient capacitance for floating diffusion, especially in three-dimensional structures, which requires reducing pixel size and complicates ensuring adequate capacitance without additional processes or area.
Innovation Solution
A transistor structure with a stack of conductive and insulating layers, including a channel layer and a gate that forms a parasitic capacitor with the second conductive layer, allowing for a floating diffusion without additional processes or area, enabling sufficient capacitance for improved image sensor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pixel size is reduced to increase integration density, then the integration density is improved, but the capacitance of the floating diffusion becomes insufficient
Solution Approach 1:
The patent utilizes the vertical dimension by forming a three-dimensional stack structure with multiple conductive layers and insulating layers. The gate electrode is positioned vertically above the channel layer, creating a vertically extended capacitor structure that increases capacitance without occupying additional horizontal pixel area, thus resolving the contradiction between integration density and floating diffusion capacitance
Solution Approach 2:
The patent implements a nested structure where the gate electrode is formed within the vertical stack, with the gate insulating layer nested between the gate electrode and the channel layer. This nested configuration allows the capacitor to be integrated within the existing transistor structure, maximizing space utilization and maintaining sufficient capacitance in reduced pixel sizes
2Quantity of substance
If additional processes or area are used to ensure sufficient capacitance, then the capacitance of the floating diffusion is improved, but the device complexity and manufacturing process increase
Solution Approach 1:
The patent merges the capacitor structure with the transistor structure by forming them as an integrated three-dimensional stack. The gate electrode serves dual purposes: as the gate for the transistor and as one plate of the capacitor, while the second conductive layer serves as the other plate. This merging eliminates the need for separate capacitor fabrication processes and reduces overall device complexity
Solution Approach 2:
The gate electrode structure is designed to perform multiple functions: it acts as the control gate for the transistor operation and simultaneously serves as one of the capacitor plates for the floating diffusion. This multi-functionality reduces the number of additional structures and processes needed, simplifying the manufacturing process while ensuring sufficient capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides a floating diffusion with sufficient capacitance using a parasitic capacitor, enhancing image sensor performance without requiring separate additional processes or area, thus supporting increased integration density without compromising fill factor.
Implementation Method 1
a gate formed on the channel layer and including a first region, formed in the open portion, and a second region overlapping the second conductive layer. The second conductive layer and the second region of the gate may form a capacitor.
Data Source
AI summary
An image sensor includes: a light receiving section suitable for generating photocharges in response to incident light; and a driving section including a source follower transistor suitable for generating an output voltage corresponding to a reference voltage in response to the photocharges. The source follower transistor includes: a stack structure formed by sequentially stacking a first conductive layer, an insulating layer and a second conductive layer; an open portion formed through the second conductive layer and the insulating layer so as to expose the first conductive layer; a channel layer formed along the surface of the open portion so as to be connected to the first conductive layer and the second conductive layer; and a gate is connected to the light receiving section and which is formed over the channel layer so as to overlap the second conductive layer.