Image Sensor Package Interconnect Layout Without TSV Stress
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Solution Overview
Problem
Current semiconductor packages with through silicon vias (TSVs) face issues such as thermal and mechanical stress, die pad damage, and large pad pitches due to the formation of TSVs, leading to failures in image sensor chip scale packages.
Innovation Solution
The implementation of semiconductor packages using interconnect bumps and multiple redistribution layers (RDLs) eliminates the need for TSVs by providing mechanical and electrical connections between die pads and outer terminals, allowing for smaller pad pitches and reducing stress, with angled sidewalls and optically transmissive lids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) are used to provide electrical interconnection, then electrical connection between front side metal pads and backside outer terminals is achieved, but thermal and mechanical stress increases and die pad damage occurs
Solution Approach 1:
The patent divides the electrical interconnection path into multiple segments: front side metal pads connect to bumps, which connect to redistribution layers (RDLs), which then connect to backside outer terminals. This segmentation eliminates the need for through silicon vias that penetrate the entire die thickness, thereby reducing thermal and mechanical stress concentration while maintaining reliable electrical interconnection.
Solution Approach 2:
The patent introduces redistribution layers (RDLs) as intermediary structures between the bumps and backside outer terminals. These RDLs serve as mediator elements that distribute electrical signals and reduce stress transmission, preventing direct stress pathways that would exist with TSVs while enabling flexible routing and connection.
2Reliability
If through silicon vias (TSVs) are formed, then electrical interconnection is provided, but die pad damage occurs during formation process
Solution Approach 1:
The patent extracts the harmful through-silicon-via formation process from the interconnection architecture. Instead of creating vias that penetrate through the die and require etching, deposition, and planarization steps that can damage die pads, the invention uses surface-level bumps and redistribution layers that connect without requiring invasive through-die processing, thereby preserving die pad integrity.
3Reliability
If through silicon vias (TSV) formation process is used, then electrical interconnection is achieved, but pad pitch becomes large
Solution Approach 1:
The patent transitions from a vertical through-die connection approach (TSVs) to a multi-layer planar approach using redistribution layers (RDLs). By adding the dimensional aspect of multiple copper layers with vias connecting them, the design achieves fine pitch routing in the lateral plane without requiring small, stress-prone through-silicon vias, thereby reducing effective pad pitch while maintaining connection reliability.
Data Source
AI summary
Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side and an active area on the second side of the die. The semiconductor packages may also include two or more bumps coupled to two or more die pads on a second side of the die. The semiconductor packages may include an optically transmissive lid coupled to the semiconductor die through an adhesive, two or more bumps, and a first redistribution layer (RDL). The semiconductor package may include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. The first RDL may extend to an edge of the semiconductor die.