Solid-State Image Sensor ADC With Two-Phase Ramp Conversion
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Solution Overview
Problem
Existing solid-state imaging devices face challenges in improving analog-to-digital conversion resolution without increasing counter rates or prolonging comparison signal shift times, which hinders frame rate and conversion bit number.
Innovation Solution
A solid-state imaging device with a comparison signal generator that produces linear and continuous comparison signals, allowing for simultaneous analog-to-digital conversion in two phases (ADC period-A and ADC period-B) using single-slope ramp waveform signals, effectively doubling the frame rate while maintaining the same conversion bit number.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the counter rate of the counter circuit is increased to improve analog-to-digital conversion resolution, then the conversion bit number increases, but the device complexity and power consumption increase
Solution Approach 1:
The patent divides the analog-to-digital conversion process into two separate phases (ADC period-A and ADC period-B), each handling different bit ranges. The first analog-to-digital converter circuit processes upper bits while the second processes lower bits, allowing each circuit to use a moderate counter rate rather than requiring one high-speed counter for all bits. This segmentation resolves the contradiction by achieving high resolution without requiring a single high-complexity counter circuit.
2Measurement precision
If the time of the shift in the voltage value of the comparison signal is prolonged to improve analog-to-digital conversion resolution, then the conversion bit number increases, but the frame rate decreases
Solution Approach 1:
The patent segments the comparison signal generation into two phases with different time ranges. The first comparison signal generator operates during ADC period-A for upper bit conversion, and the second comparison signal generator operates during ADC period-B for lower bit conversion. This allows the system to achieve high resolution without requiring a single prolonged comparison signal time, thereby maintaining high frame rate.
Solution Approach 2:
The patent implements periodic action by conducting two separate analog-to-digital conversion phases in succession. Each phase uses its own comparison signal with appropriate time duration for the specific bit range being converted. This periodic structure allows the system to complete high-resolution conversion without requiring any single comparison signal to be prolonged, thus maintaining high frame rate.
3Productivity
If pipeline operation is performed to increase throughput, then the processing capacity improves, but the device complexity increases
Solution Approach 1:
The patent divides the analog-to-digital converter into two separate converter circuits operating in parallel for different bit ranges. The first converter circuit handles upper bits and the second converter circuit handles lower bits. This segmentation provides pipeline-like throughput improvement without requiring a complex multi-stage pipeline structure, as each converter circuit is relatively simple and operates independently.
Data Source
AI summary
Pixels, a charge storage element, a comparison signal generator that generates comparison signals, and a first analog-to-digital converter circuit that performs analog-to-digital conversion are included. The comparison signal generator generates the comparison signals such that a waveform having a voltage value that ranges from an upper limit to a lower limit and that has linearity and continuity is formed by connecting waveforms of the comparison signals to each other.