Image Sensor Parallel Vertical Output Lines Readout Speed

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing solid-state image sensing apparatuses have limitations in shortening the total readout period from the pixel array to multiple differential amplifiers, due to sequential signal transfer paths and delays in signal processing, which hinder the reduction of the overall readout time.

Innovation Solution

The image sensor design includes a pixel unit array with parallel transfer operations to two holding blocks via separate vertical output lines, allowing simultaneous signal transfer and processing, thereby reducing the total readout period by enabling concurrent horizontal transfer operations to multiple output amplifiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If sequential signal transfer paths are used from pixel array to multiple differential amplifiers, then device complexity is reduced, but readout time increases

Engineering Contradiction:
Improvereadout periodVSAvoidsignal transfer path structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The pixel array is divided into multiple regions (first pixel units and second pixel units) with different color filter configurations. Each region has dedicated vertical output lines and holding blocks, creating parallel signal transfer paths that reduce the total readout period by enabling simultaneous readout from multiple regions

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to the readout process by enabling parallel operations. Multiple holding blocks receive signals simultaneously from different pixel unit regions through separate vertical output lines, and multiple differential amplifiers process signals concurrently, transforming sequential readout into parallel readout across multiple dimensions

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If parallel vertical output lines are used for simultaneous signal transfer, then readout speed increases, but device complexity increases

Engineering Contradiction:
Improvereadout speedVSAvoidvertical output line structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Vertical output lines are segmented into multiple independent lines (first vertical output lines and second vertical output lines), each dedicated to specific pixel unit regions. This segmentation enables parallel signal transfer without interference, increasing readout speed while maintaining structured organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Holding blocks serve as intermediary elements between the parallel vertical output lines and the differential amplifiers. Each holding block receives signals from specific vertical output lines and transfers them to differential amplifiers, mediating the parallel signal flow and enabling coordinated readout operations

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple holding blocks and output amplifiers are used for parallel processing, then productivity increases, but device complexity increases

Engineering Contradiction:
Improvesignal processing throughputVSAvoidholding block and amplifier structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The signal processing system is segmented into multiple independent processing channels, each consisting of a holding block and a differential amplifier. First holding blocks and second holding blocks process signals from different pixel unit regions independently, with corresponding differential amplifiers performing parallel readout operations, thereby increasing overall processing throughput

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The holding blocks and differential amplifiers are designed with universal functionality to handle different types of signals from various pixel unit regions. Each holding block can store signals from multiple vertical output lines, and each differential amplifier can process signals from multiple holding blocks, enabling flexible and efficient parallel processing

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9294744B2Image sensor and image sensing apparatus with plural vertical output lines
Publication Date: 2016.03.22 CANON KK
  • US9294744B2 patent drawing
  • US9294744B2 patent drawing
  • US9294744B2 patent drawing

AI summary

An image sensor comprises: a pixel unit array; a driving unit; a second holding block; a first output amplifier; and a second output amplifier, each column of the pixel unit array including a plurality of first pixel units and a plurality of second pixel units, wherein the driving unit drives the pixel unit array to parallel-perform, on each column of the pixel unit array, an operation to transfer signals from the first pixel units to the first holding block via the first vertical output line, and an operation to transfer signals from the second pixel units to the second holding block via the second vertical output line.