Image Sensor Package Vertical Stack Power Integrity
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Solution Overview
Problem
Existing image sensors face limitations due to lengthened interconnection paths and limited interconnection space, which adversely affect power integrity and other characteristics.
Innovation Solution
An image sensor package design featuring a vertically stacked configuration of an image sensor chip, logic chip, and memory chip, with through mold vias (TMVs) and through silicon vias (TSVs) for efficient signal and power distribution, and a redistribution structure to optimize power integrity and signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar layout is used for image sensor components, then manufacturing is simpler, but interconnection paths become lengthened and interconnection space is limited, adversely affecting power integrity
Solution Approach 1:
The patent transitions from a conventional planar (2D) layout to a three-dimensional stacked architecture, where the image sensor chip, logic chip, and memory chip are vertically arranged. This dimensional change dramatically shortens interconnection paths by eliminating long lateral traces, as components that were previously separated across large planar distances are now positioned directly above or below each other, connected through vertical vias and TSVs.
Solution Approach 2:
The patent implements a nested hierarchical structure where multiple functional chips are stacked and interconnected through vertical pathways. The logic chip is positioned above the image sensor chip, and the memory chip is positioned above the logic chip, with each layer nested within the overall vertical stack. This nesting enables compact integration while maintaining short interconnection paths through the use of through-silicon vias and redistribution layers.
2Adaptability or versatility
If more interconnection structures are added to improve signal distribution, then connectivity improves, but interconnection space becomes limited and device complexity increases
Solution Approach 1:
The patent resolves the space constraint by moving interconnection structures from the lateral plane to the vertical dimension. Through-silicon vias (TSVs) and vertical interlayer via structures enable signals to travel vertically between stacked chips, effectively utilizing the third dimension for interconnection. This approach provides high connectivity without consuming additional planar area, as the interconnection pathways are established through the thickness of the chips rather than across their surfaces.
Data Source
AI summary
An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.