Image Sensor Vertical Transistor Integration for High Fill Factor
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Solution Overview
Problem
Current image sensors face challenges in maximizing the fill factor and maintaining sensor characteristics while reducing the physical size of unit pixels to increase pixel density, leading to degraded pixel characteristics.
Innovation Solution
The image sensor design includes a vertically stacked structure with a photoelectric conversion element and pixel transistors, featuring a transfer transistor with a vertical channel, and thin film transistors for the reset, drive, and selection transistors, which share channel layers to enhance efficiency and integration density without compromising sensor sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the physical size of unit pixels is reduced to increase pixel density, then the pixel density increases, but the sensor characteristics deteriorate
Solution Approach 1:
The patent transitions from a planar transistor layout to a vertical three-dimensional structure. The transfer transistor is formed with a vertical channel extending through the photoelectric conversion element, while reset, drive, and selection transistors are stacked vertically using thin-film transistor structures. This vertical integration allows multiple transistors to occupy a smaller footprint area, increasing pixel density without compromising the photoelectric conversion area or sensor characteristics.
2Quantity of substance
If the physical size of unit pixels is reduced, then more pixels can be integrated in limited area, but the fill factor cannot be maximized
Solution Approach 1:
The patent employs vertical stacking of transistors along the z-axis to reduce the horizontal footprint of each pixel. The transfer gate extends vertically through the photoelectric conversion element, and other transistors are stacked above the substrate plane. This three-dimensional arrangement maximizes the photoelectric conversion area in the horizontal plane while accommodating all necessary transistors in the vertical dimension, thereby maintaining a high fill factor.
3Productivity
If vertically stacked structure with shared channel layers is used, then integration efficiency is enhanced, but device complexity increases
Solution Approach 1:
The patent merges multiple transistor functions by having the transfer, reset, drive, and selection transistors share common channel layers. The thin-film transistor structures utilize shared gate dielectric layers and channel layers, reducing the number of discrete layers compared to fully independent transistor structures. This merging approach simplifies the fabrication process and reduces overall structural complexity while achieving high integration efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a high fill factor and maintains sensor sensitivity by effectively integrating more unit pixels in a limited area, preventing deterioration in sensor characteristics despite reduced pixel size, and allows for improved image quality.
Implementation Method 1
a substrate including a photoelectric conversion element
Data Source
AI summary
An image sensor may include: a substrate including a photoelectric conversion element; a first interlayer dielectric layer formed over the photoelectric conversion element; a channel layer including a first region and a second region, the first region being formed in an opening passing through the first interlayer dielectric layer, with a portion of the first region contacting the photoelectric conversion element, and the second region being formed over the first interlayer dielectric layer; a transfer transistor formed over the first region of the channel layer, the transfer transistor including a transfer gate which gapfills the opening; and a reset transistor including a reset gate formed over the second region of the channel layer.