Image Sensor Conductive Vias Segmentation for Short Circuit Prevention
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Solution Overview
Problem
In the manufacturing of image sensor devices, the electrical performance of through oxide vias is hindered by short circuits and planarity issues due to the large surface area of conductive vias, leading to reduced signal propagation across the 'TOV' area.
Innovation Solution
A composite capping structure is formed with electrically isolated conductive pads covering the conductive vias, ensuring electrical isolation and preventing short circuits, while a protective dielectric fills spaces between the pads to enhance planarity and maintain electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the surface area of conductive vias is increased to ensure reliable contact, then electrical connection reliability is improved, but short circuit risk and planarity issues worsen
Solution Approach 1:
The conductive via array is segmented into individually capped vias, with each via covered by its own isolated capping pad. This segmentation prevents short circuits between adjacent vias while maintaining reliable electrical connection for each individual via, resolving the contradiction between connection reliability and short circuit risk
Solution Approach 2:
A dielectric layer is introduced as an intermediary material between adjacent conductive vias. This dielectric layer provides electrical isolation and prevents short circuits while allowing each via to maintain its own electrical connection, thus resolving the contradiction between reliable contact and short circuit prevention
2Reliability
If the surface area of conductive vias is increased to ensure reliable contact, then electrical connection reliability is improved, but planarity issues worsen
Solution Approach 1:
The array of conductive vias is segmented into individually capped structures. Each via is covered by a separate capping pad that can be precisely controlled in height and position, allowing planarity to be maintained across the entire array while each via maintains sufficient surface area for reliable electrical connection
Solution Approach 2:
Each conductive via is provided with localized capping structure that ensures uniform height and planarity across the entire via array. The local quality of each capped via is optimized independently, allowing the overall array to achieve high planarity while maintaining reliable electrical connection for each individual via
Data Source
AI summary
The present disclosure provides a method of manufacturing an image sensor device. The method comprises forming a first semiconductor chip including a matrix of image sensing cells and bonding a second semiconductor chip with the first semiconductor chip. A plurality of conductive vias are formed in the second semiconductor chip, where each of the plurality of conductive vias includes a first end substantially coplanar with a first surface of the first semiconductor chip and a second end in contact with a conductive trace in the second semiconductor chip. A first dielectric layer is formed over the plurality of conductive vias and a first conductive material is formed over the first dielectric layer. The first conductive material is etched to form a plurality of conductors coupled to ground and the plurality of conductors are electrically isolated from one another.