Solid-State Image Sensor Wiring Layer Design
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Solution Overview
Problem
Conventional solid-state image sensors require multiple conductor layers in the wiring layer, which complicates the layout and increases costs without effectively reducing the number of layers, affecting light reception and balance with peripheral circuits.
Innovation Solution
A solid-state image sensor with a wiring layer that uses only two conductor layers, where power supply wires are placed near the semiconductor substrate and driving signal wires are placed away from it, allowing for improved design freedom and reduced manufacturing processes without adverse effects on light reception.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the number of conductor layers is reduced to achieve cost reduction, then manufacturing cost decreases, but layout flexibility and balance with peripheral circuits deteriorate
Solution Approach 1:
The patent applies dimensional change by transitioning from a planar wiring layout to a three-dimensional stacked configuration. Multiple conductor layers are arranged vertically above the pixel array, allowing wirings to be distributed across different height levels. This vertical arrangement provides layout flexibility equivalent to having more horizontal layers, while actually using fewer conductor layers, thus reducing manufacturing cost while maintaining design freedom.
Solution Approach 2:
The wiring layer is segmented into multiple functional regions across different conductor layers. Power supply wirings, signal wirings, and control wirings are separated into distinct layers, allowing independent optimization of each wiring type. This segmentation enables effective layout design with reduced number of layers by assigning specific functions to specific vertical positions.
2Adaptability or versatility
If more conductor layers are used to improve wiring layout flexibility, then design freedom increases, but device complexity and manufacturing processes increase
Solution Approach 1:
The patent utilizes the vertical dimension to achieve wiring layout flexibility that would otherwise require multiple horizontal layers. By arranging conductor layers stacked in the vertical direction above the pixel array, the design obtains three-dimensional wiring freedom without increasing the planar footprint or the total number of conductor layers, thus reducing device complexity.
Solution Approach 2:
Each conductor layer is designed to serve multiple functions simultaneously. For example, certain layers carry both power supply signals and control signals, or serve as both signal transmission paths and shielding layers. This multi-functionality reduces the total number of conductor layers needed while maintaining comprehensive wiring capabilities.
3Ease of manufacture
If conductor layers are reduced to simplify manufacturing, then manufacturing processes decrease, but wiring functionality and performance may be compromised
Solution Approach 1:
The patent compensates for reduced conductor layer count by exploiting vertical spatial arrangement. Wirings are positioned at optimized vertical heights to minimize interference with light reception while maintaining electrical functionality. This three-dimensional positioning ensures that essential wiring functions are preserved even with fewer layers, maintaining reliability while simplifying manufacturing.
Solution Approach 2:
Different regions of the wiring layer are assigned different qualities and functions based on local requirements. Areas above pixel regions use specific conductor configurations optimized for light transmission, while areas above peripheral circuits use configurations optimized for signal routing. This localized optimization maintains wiring functionality throughout the device despite reduced overall layer count.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the number of conductor layers, minimizing the impact on light reception and reducing manufacturing costs while maintaining high performance.
Implementation Method 1
a plurality of pixels each having a photoelectric conversion element are arranged
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers.