Stacked Image Sensor Wiring Layout for Stable Reference Potential
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Solution Overview
Problem
Existing photoelectric conversion apparatuses lack a clear layout of wiring patterns for supplying reference potentials in pixel and peripheral regions, leading to potential fluctuations and degradation of image quality due to coupling and voltage drop.
Innovation Solution
A stacked chip configuration with a first and second semiconductor element layer, featuring a trench for reference potential supply and a higher wiring density in the pixel region compared to the peripheral region, with specific wiring patterns to minimize voltage drop and coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wiring patterns for reference potential are supplied in pixel region and peripheral region with uniform layout, then manufacturing is simplified, but impedance increases and potential fluctuations occur leading to image quality degradation
Solution Approach 1:
The patent applies local quality by differentiating the wiring pattern layout between the pixel region and peripheral region. In the pixel region, wiring patterns are arranged with higher density and specific orientations to reduce impedance and potential fluctuations that would otherwise degrade image quality. In the peripheral region, a different layout is used that is optimized for its functional requirements. This localized differentiation resolves the contradiction by improving image quality through region-specific optimization while managing overall device complexity through systematic variation rather than uniform complexity throughout.
2Reliability
If wiring density is increased in pixel region to reduce impedance and potential fluctuations, then image quality improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the wiring pattern parameters (density, orientation, spacing) between different regions. In the pixel region, wiring density is increased and specific geometric parameters are adjusted to reduce impedance and potential fluctuations, thereby improving image quality. The manufacturing precision challenge is addressed by establishing consistent design rules and parameters that can be controlled during fabrication. The parameter variations are implemented in a systematic manner that balances performance improvement with manufacturability.
Data Source
AI summary
A photoelectric conversion apparatus according to an embodiment includes a first chip and a second chip. The first chip includes a first semiconductor element layer having a pixel region having pixel circuits and a peripheral region and a first wiring structure including a first wiring layer. The second chip includes a second semiconductor element layer having an electric circuit and a second wiring structure. The first and second chips are stacked, and have a trench extending through the first semiconductor element layer and having a pad through which a reference potential is supplied to the pixel circuits. The first wiring layer includes a first wiring pattern to which the reference potential is supplied. In plan view, the first wiring pattern located in a region aligned with the pixel region has a higher wiring density than the first wiring pattern located in a region aligned with the peripheral region.