Image Signal Processing Apparatus Reducing Display Delay
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Solution Overview
Problem
Conventional image pickup apparatuses and display devices experience significant display delay when showing real-time images, particularly due to increased pixel counts and image quality improvements, leading to awkward user experiences during operations like panning and zooming.
Innovation Solution
The implementation of a configuration that includes a first image reduction unit, memory for storing reduced images, an external output unit, a display, a second image reduction unit for direct display size reduction without memory storage, and a signal processor for real-time signal processing to synchronize image frequencies, reducing display delay by processing and displaying images within one frame time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If image quality improvement functions are performed with increased pixel counts, then image quality is improved, but signal processing time increases causing display delay
Solution Approach 1:
The patent segments the image processing pipeline into distinct functional units: a first image reduction unit for initial downsampling, a memory for buffering, a second image reduction unit for display-size reduction, and a signal processor for final processing. This segmentation allows parallel processing paths where the first reduction unit processes images independently of the display frame rate, enabling quality processing without delaying display output.
Solution Approach 2:
The first image reduction unit performs preliminary downsampling of the captured image before it enters the main processing pipeline. By reducing the image size early in the process, subsequent processing steps operate on smaller data sets, significantly reducing total processing time and enabling display output to keep pace with the frame rate without compromising final image quality.
2Productivity
If frame frequency is reduced, then processing load is decreased, but display delay amount increases
Solution Approach 1:
The system dynamically adapts the frame frequency of the display output independently from the image capture and processing frame rates. The controller adjusts the display frame frequency to match the processing capability of the segmented pipeline, allowing the system to maintain high processing throughput while minimizing display delay. This dynamic adjustment ensures the display operates at the maximum sustainable frame rate without becoming a bottleneck.
3Device complexity
If conventional video display device configuration is used, then device complexity is reduced, but display delay time increases to one frame or more
Solution Approach 1:
The patent introduces a memory buffer as an intermediary element between the image capture unit and the display output. This buffer decouples the capture frame rate from the display frame rate, allowing images to be processed and prepared in advance without waiting for display synchronization. The memory acts as a mediator that absorbs timing differences and enables the display to output images with minimal delay while maintaining system simplicity.
Data Source
AI summary
An image pickup apparatus includes a first image reduction unit configured to reduce the size of an image output by an image pickup element, a memory configured to store the image reduced by the first image reduction unit, an external output unit configured to output the image stored in the memory, a display configured to display an image being shot, a second image reduction unit configured to reduce, to the display size on the display, the image reduced by the first image reduction unit, without causing the reduced image to be stored in the memory and a signal processor for the display configured to perform signal processing of the image reduced to the display size on the display.