Image Signal Processing Apparatus Dynamic Bit Compression

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Solution Overview

Problem

Organic light emitting display devices experience decreased display quality over time due to transistor and organic light emitting diode deterioration, leading to image signal processing challenges.

Innovation Solution

An image signal processing apparatus that includes an adder, analyzing block, processing block, encoding block, memory, decoding block, and inverse processing block to cumulate, process, compress, and restore image data signals, minimizing information loss and improving display quality by detecting valid most significant bits and adjusting bit shifts and data deletion based on critical values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the cumulative data signal is compressed by deleting lower bits, then the compression ratio is increased and memory size is reduced, but information loss increases and display quality deteriorates

Engineering Contradiction:
Improvecompression ratioVSAvoidinformation loss
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent applies dynamic processing by detecting the valid most significant bit position and adjusting the bit deletion strategy accordingly. Instead of fixed compression, the system dynamically determines how many lower bits to delete based on the actual data characteristics, allowing optimal balance between compression ratio and information preservation for each frame

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies local quality by treating different bit positions differently. The valid most significant bits are preserved while lower bits are selectively deleted. This local differentiation ensures that important information (higher bits) is retained while less critical information (lower bits) is compressed, achieving both compression and quality maintenance

Inventive Principle:
Principle #3Local quality

2Measurement precision

If the valid most significant bit is detected at every frame, then the processing precision is improved, but the processing time and complexity increase

Engineering Contradiction:
Improveprocessing precisionVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies periodic action by detecting the valid most significant bit at predetermined intervals (every N frames) rather than at every single frame. This periodic detection maintains sufficient processing precision while significantly reducing the frequency of complex operations, thus lowering overall processing time and computational burden

Inventive Principle:
Principle #19Periodic action

3Productivity

If bit-shifting is applied to process the cumulative data signal, then the compression efficiency is improved, but the circuit complexity increases

Engineering Contradiction:
Improvecompression efficiencyVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces complex mechanical or hardware-based signal processing mechanisms with software or algorithmic bit-shifting operations. By using logical bit-shift instructions to process the cumulative data signal, the system achieves efficient compression without requiring complex dedicated hardware circuits, thus improving compression efficiency while keeping circuit complexity low

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10313678B2Image signal processing apparatus and display device having the same
Publication Date: 2019.06.04 SAMSUNG DISPLAY CO LTD
  • US10313678B2 patent drawing
  • US10313678B2 patent drawing
  • US10313678B2 patent drawing

AI summary

An image signal processing apparatus includes an adder to add an input data signal of a present frame to a cumulative data signal of a previous frame to output a cumulative data signal, an analyzing block to analyze a processing range of the cumulative data signal, a processing block to process the cumulative data signal based on the processing range to output a processed data signal, an encoding block to compress the processed data signal to output an encoded data signal, a memory to store the encoded data signal and the processing range, a decoding block to decode the encoded data signal read out from the memory to output a decoded data signal, and an inverse processing block to inversely process the decoded data signal based on the processing range to output an output data signal.