Imager ADC Gain Switching for Low-Noise Constant-Time Sampling
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Solution Overview
Problem
Conventional analog-to-digital converters in imaging systems suffer from temporal noise, leading to reduced imaging accuracy, and increasing operational time or ramp signal slope to reduce noise results in processing delays or increased power consumption.
Innovation Solution
The implementation of improved analog-to-digital converter circuitry that adjusts the number of samples taken based on light conditions, using different gain modes with constant total operational time, and applying offset voltages to maintain full resolution, allowing for reduced noise without increasing processing time or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple digital samples are collected and averaged to reduce temporal noise, then imaging accuracy is improved, but ADC operational time increases causing processing delays
Solution Approach 1:
The patent implements dynamic gain mode selection that adapts to light conditions. The system switches between different gain modes (first gain mode with longer integration time, second gain mode with shorter integration time) based on whether light conditions are below or above a threshold. This dynamic adaptation allows the system to collect multiple samples for noise reduction only when necessary (in low light), thereby improving imaging accuracy without incurring processing delays in all conditions.
Solution Approach 2:
The patent changes the integration time parameter dynamically by switching between different gain modes. In the first gain mode, a longer integration time is used to collect multiple digital samples for averaging, reducing temporal noise. In the second gain mode, a shorter integration time is used when sufficient light is available, maintaining processing speed. This parameter change resolves the contradiction between noise reduction and processing delay.
2Productivity
If ramp signal slope is increased to reduce ADC operational time, then processing speed is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the ramp signal slope by switching between gain modes. In the first gain mode, a slower ramp slope is used with longer integration time to collect multiple samples. In the second gain mode, a faster ramp slope is used with shorter integration time when light conditions permit. This dynamic adjustment optimizes the balance between processing speed and power consumption based on actual imaging conditions.
Solution Approach 2:
The patent employs periodic switching between different gain modes based on light condition thresholds. The system periodically evaluates light conditions and switches between operational modes, using higher ramp slopes (faster processing) only when light conditions are sufficient, thereby reducing overall power consumption while maintaining acceptable processing speeds.
3Measurement precision
If multiple samples are collected using conventional ADC circuitry, then temporal noise is reduced, but the amount of ADC operational time doubles
Solution Approach 1:
The patent implements dynamic gain mode switching that adapts the number of samples collected to light conditions. In the first gain mode (low light), multiple samples are collected and averaged to reduce temporal noise. In the second gain mode (sufficient light), fewer samples are collected, reducing ADC operational time. This dynamic approach ensures temporal noise reduction is applied only when necessary, avoiding doubled operational time in all conditions.
Solution Approach 2:
The system changes the sampling parameter dynamically by switching between gain modes. The first gain mode configures the ADC to collect multiple samples with longer integration time for noise reduction. The second gain mode reduces the number of samples and shortens integration time when light conditions are sufficient. This parameter change resolves the contradiction between temporal noise reduction and ADC operational time.
Data Source
AI summary
An imager may include analog-to-digital converter circuitry that converts an analog input voltage to a digital output value by generating a number of samples of the analog input voltage. The analog input voltage may be formed from the difference between a pixel signal and a reference signal received at first and second inputs of the analog-to-digital converter circuitry. Processing circuitry may control the number of samples generated from the analog input voltage based on a desired gain level. The analog-to-digital converter circuitry may include a counter that counts to a maximum value. Ramp generation circuitry may generate a ramp signal based on the counter value and apply the ramp signal to the pixel signal at the first input of the analog-to-digital converter circuitry. The total time for generating samples for each different desired gain level may be constant while generating the ramp signal with a slope having a constant magnitude.