Imager Gate Stack Sidewall Spacers for Electrical Isolation
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Solution Overview
Problem
Conventional microelectronic imager devices exhibit structural and operational deficiencies, such as inefficiency, reliability issues, and durability concerns, which affect their performance and image capture capabilities.
Innovation Solution
The method involves forming gate stack sidewall spacers with a dual structure of nitride and oxide materials in the peripheral region of imager devices, while using only oxide materials in the sensor array region, to enhance electrical isolation and prevent shorting, and by forming silicide layers on polysilicon material in the peripheral region to reduce resistance and increase switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate stack sidewall spacers are used in both sensor array and peripheral regions, then manufacturing simplicity is maintained, but electrical isolation is insufficient leading to shorting and reliability issues
Solution Approach 1:
The patent applies different sidewall spacer structures to different regions: the sensor array region uses a first sidewall spacer structure while the peripheral region uses a second sidewall spacer structure. This local differentiation provides enhanced electrical isolation in the peripheral region where shorting risks are higher, while maintaining manufacturing efficiency by using standard structures in the sensor array region.
2Speed
If uniform sidewall spacer structures are used throughout the device, then manufacturing process simplicity is maintained, but switching speed and resistance performance are suboptimal
Solution Approach 1:
The patent implements region-specific sidewall spacer configurations where the peripheral region receives a second sidewall spacer structure with different properties than the first sidewall spacer structure used in the sensor array. This enables optimized switching speed and resistance characteristics in the peripheral region while maintaining ease of manufacture through standardized processes applied to the sensor array region.
3Reliability
If simple sidewall spacer structures are used, then manufacturing ease is maintained, but dark current and signal-to-noise ratio degradation occur
Solution Approach 1:
The patent differentiates sidewall spacer structures between regions: the sensor array region uses a first sidewall spacer structure that minimizes interference with photo detection, while the peripheral region uses a second sidewall spacer structure that provides enhanced electrical isolation. This local optimization reduces dark current and improves signal-to-noise ratio without excessive complexity.
Data Source
AI summary
Imager devices have a sensor array and a peripheral region at least partially surrounding the sensor array. At least one transistor in the peripheral region has a gate stack sidewall spacer that differs in composition from a gate stack sidewall spacer on at least one transistor in the sensor array. Imaging systems include such an imager device configured to communicate electrically with at least one electronic signal processor and at least one memory storage device. Methods of forming such imager devices include providing layers of oxide and nitride materials over transistors on a workpiece, and using etching processes to form gate stack sidewall spacers on the transistors.