Imager Pixel Charge Collection Region Vertical Architecture
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Solution Overview
Problem
Conventional CMOS imagers with pinned photodiodes face reduced charge handling capacity and increased electrical cross-talk due to reduced power supply, leading to limited depletion width and increased lateral carrier diffusion, especially in deep sub-micron technology and back-illuminated designs.
Innovation Solution
The implementation of a pixel structure with specific semiconductor layers and a charge collection region extending vertically, along with a transfer gate and insulating regions, allows for controlled depletion and reduced cross-talk by channeling carriers vertically rather than laterally, enhancing charge storage and handling capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional pinned photodiode structure is used in deep sub-micron technology, then device complexity is reduced, but charge handling capacity is reduced and electrical cross-talk increases
Solution Approach 1:
The pixel structure is segmented into multiple semiconductor layers (first through fourth layers with alternating conductivity types) with distinct functional regions. The charge collection region is specifically positioned within the third and fourth layers, separating charge collection functions from other pixel operations, thereby improving charge handling capacity while maintaining manageable device complexity.
Solution Approach 2:
The invention transitions from a conventional planar pinned photodiode structure to a multi-layer vertical architecture. The charge collection region extends vertically through the third and fourth semiconductor layers, utilizing the vertical dimension to increase charge handling capacity without increasing lateral pixel area, thus resolving the contradiction between device complexity and charge handling capacity.
2Use of energy by moving object
If reduced power supply is used for deep sub-micron operation, then power consumption is reduced, but depletion width is reduced leading to increased cross-talk
Solution Approach 1:
The charge collection region is positioned vertically within the third and fourth semiconductor layers, extending in the depth direction rather than laterally. This vertical arrangement allows carriers to be collected along the vertical path, reducing lateral diffusion and electrical cross-talk between adjacent pixels, thereby resolving the cross-talk issue while maintaining reduced power supply operation.
Solution Approach 2:
The pixel structure implements localized doping regions with specific conductivity types in different layers. The charge collection region has tailored doping characteristics positioned within the third and fourth layers, creating localized electric fields that guide carriers vertically and reduce lateral diffusion, thus reducing cross-talk while operating at reduced power supply voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces cross-talk and improves charge handling capacity by ensuring carriers are collected efficiently within the charge collection region, thereby improving the performance of imagers under reduced power supply conditions.
Implementation Method 1
a charge collection region of the second conductivity type formed inside the third semiconductor layer and the fourth semiconductor layer and extending vertically to a second depth from the pixel front side
Implementation Method 2
there is a higher likelihood that the charges generated within the imager diffuse laterally and this results in a worse inter-pixel cross-talk
Data Source
AI summary
Pixels, imagers and related fabrication methods are described. The described methods result in cross-talk reduction in imagers and related devices by generating depletion regions. The devices can also be used with electronic circuits for imaging applications.