Imaging Sensor D/A Buffer Circuit for Reference Noise Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Manufacturing variations in the buffer circuit of digital-to-analog conversion circuits in solid-state imaging devices lead to noise generation, particularly in dark environments, due to the large capacitance of external capacitive elements and size constraints of transistors, resulting in inaccurate A/D conversion and image quality deterioration.
Innovation Solution
A solid-state imaging device with a D/A conversion circuit that includes a differential pair circuit and a suppression circuit to cancel out characteristic differences between transistors, reducing noise by averaging variations through chopper operation or auto-zero circuits, allowing for smaller transistor sizes and reduced circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the transistor size is reduced to meet circuit area constraints, then the circuit area is reduced, but manufacturing variations increase causing noise generation
Solution Approach 1:
The patent implements a feedback mechanism where the buffer circuit continuously monitors and adjusts its output based on the actual characteristics of the transistors. The third transistor's gate voltage is adjusted according to the voltage difference detected between the first and second transistors, creating a closed-loop system that compensates for manufacturing variations and maintains signal stability despite size reductions
Solution Approach 2:
The patent dynamically changes the gate voltage parameter of the third transistor to compensate for manufacturing variations. By adjusting this voltage parameter based on detected differences between transistors, the system maintains consistent performance even when transistor dimensions are reduced, effectively decoupling circuit area from manufacturing precision
2Object-affected harmful factors
If external capacitive elements with large capacitance are used, then noise filtering is improved, but the D/A conversion circuit cannot be fully integrated increasing device complexity
Solution Approach 1:
The patent extracts the noise compensation function from the traditional approach of using large external capacitors and implements it within the buffer circuit itself through the third transistor. This removes the need for external capacitive elements while maintaining noise filtering capability, achieving full integration without sacrificing noise performance
Solution Approach 2:
The third transistor serves as an intermediary element that mediates between the differential pair and the output. It actively compensates for noise and manufacturing variations through controlled voltage adjustment, replacing the passive noise filtering function of external capacitors with an active integrated solution
3Area of moving object
If transistor size is reduced, then circuit area is reduced, but A/D conversion accuracy deteriorates due to increased manufacturing variations
Solution Approach 1:
The buffer circuit employs feedback to continuously monitor voltage differences caused by manufacturing variations and actively compensate for them. This feedback mechanism ensures that the reference signal maintains high precision regardless of transistor size, preserving A/D conversion accuracy in compact circuits
Solution Approach 2:
The system dynamically adjusts the gate voltage parameter of the third transistor to counteract the effects of reduced transistor size. By changing this parameter in response to detected variations, the system maintains the precision required for accurate A/D conversion while benefiting from reduced circuit area
Data Source
AI summary
A solid-state imaging device includes: a pixel unit that outputs a pixel signal corresponding to an amount of incident light; an A/D converter that performs A/D conversion on the pixel signal; and a D/A conversion circuit that generates a reference signal to be used by the A/D converter. The D/A conversion circuit includes a first buffer circuit that outputs a base voltage VTOP for generating the reference signal, and the first buffer circuit includes a differential pair circuit including a first transistor and a second transistor, and a suppression circuit that suppresses a variation in the base voltage by canceling out a characteristic difference between the first transistor and the second transistor.