Imaging Chip Output Layout for Flexible Serial or Parallel Readout
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Solution Overview
Problem
Existing solid-state imaging devices face challenges in efficiently connecting chips and analog front ends, limiting flexibility in design and manufacturing for different usage priorities such as speed or cost, which increases design and manufacturing costs.
Innovation Solution
The solid-state imaging device is configured with a chip that includes a pixel array and multiple output circuits, allowing for flexible connection configurations between the chip and the analog front end through parallel or serial signal wire layouts, enabling independent operation of unit blocks for varied usage scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed connection configuration is used between chip and analog front end, then manufacturing process is simplified, but flexibility for different usage priorities (speed or cost) is reduced
Solution Approach 1:
The chip is divided into multiple independently operable unit blocks, each capable of being connected to the analog front end through separate signal wires. This segmentation allows selective activation of different connection configurations (parallel or serial) based on usage priorities without requiring complete redesign of the entire device
Solution Approach 2:
The connection configuration is made dynamic by allowing selection between parallel and serial signal wire layouts depending on whether speed or cost is prioritized. The system can adapt its connection mode based on operational requirements, transitioning between fixed configurations rather than being locked into a single static design
2Adaptability or versatility
If different connection configurations are designed for speed-prioritized and cost-prioritized devices, then usage flexibility is improved, but design and manufacturing costs increase
Solution Approach 1:
A single chip design incorporates multiple unit blocks that can operate in different connection modes (parallel or serial) to the analog front end. This universal design allows the same chip to serve both speed-prioritized and cost-prioritized applications by simply changing the activation pattern of unit blocks, eliminating the need for separate designs for different usage scenarios
Solution Approach 2:
The system achieves different operational characteristics by changing the activation state of unit blocks rather than changing the physical structure. By controlling which unit blocks are active and how they are connected, the same hardware can be configured for high-speed parallel operation or cost-effective serial operation, adjusting parameters through software or control logic rather than physical redesign
Data Source
AI summary
According to one embodiment, there is a solid-state imaging device including a chip. The chip includes a pixel array, a plurality of signal lines, a plurality of output circuits and a plurality of output terminals. In the pixel array, a plurality of pixel groups each including two or more pixels is arrayed at least in a column direction. The plurality of signal lines corresponds to the plurality of pixel groups, each of the plurality of signal lines being connected to a corresponding pixel group. The plurality of output circuits corresponds to the plurality of signal lines, each of the plurality of output circuits being connected to a corresponding signal line. The plurality of output terminals corresponds to the plurality of output circuits, each of the plurality of output terminals being connected to a corresponding output circuit.