Solid-State Imaging Clock Tree for Signal Reliability
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Solution Overview
Problem
Conventional column AD converters for MOS-type solid-state imaging devices face challenges in maintaining accurate clock waveforms and increasing AD conversion speed and accuracy, leading to degraded image quality and increased layout area due to high interconnect load and noise issues.
Innovation Solution
A solid-state imaging device with a ramp-type AD converter that includes a digital-to-analog conversion circuit, column comparison circuits, and counter circuits, utilizing a clock tree structure with M first inverters in the upper stage and buffers or second inverters in the lower stage to maintain clock duty and reduce the number of buffer stages, thereby improving image quality and frame rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of buffer stages is increased to delay signals over long interconnect distances, then signal transmission reliability is improved, but the layout area increases and pulse waveform accuracy deteriorates
Solution Approach 1:
The patent segments the clock distribution network into multiple hierarchical stages (first stage with buffers, second stage with buffers, third stage with inverters). This segmentation allows the system to cover long interconnect distances without requiring a single excessive number of buffer stages, thereby reducing overall layout area while maintaining signal transmission reliability.
Solution Approach 2:
The patent introduces a hierarchical dimension to the clock distribution system by organizing buffers and inverters into multiple stages with different fan-out capabilities. This dimensional organization allows efficient signal distribution over long distances without linearly increasing the number of components, thus reducing layout area while maintaining reliability.
2Reliability
If the number of buffer stages is increased to cover long interconnect distances, then signal transmission reliability is improved, but pulse waveform accuracy deteriorates due to cumulative delay
Solution Approach 1:
The patent segments the clock distribution into hierarchical stages where each stage has controlled buffer/inverter counts. This segmentation limits the cumulative delay effect in any single path while still covering long interconnect distances through multiple stages, thereby maintaining pulse waveform accuracy (H-width and L-width balance) while ensuring signal transmission reliability.
Solution Approach 2:
The patent applies different device types (buffers vs. inverters) at different hierarchical stages based on local requirements. First and second stages use buffers for high fan-out distribution, while the third stage uses inverters for fine-tuned signal conditioning. This local quality differentiation optimizes both signal transmission reliability and pulse waveform accuracy at each stage.
3Productivity
If clock frequency is increased to improve AD conversion speed, then productivity is improved, but generated noise increases
Solution Approach 1:
The patent introduces a hierarchical clock distribution system with multiple stages of buffers and inverters as intermediaries between the clock source and the AD converters. These intermediaries isolate and filter noise generated by high-frequency operation, allowing high clock frequencies (improving AD conversion speed) while preventing noise propagation that would degrade image quality.
4Quantity of substance
If the number of columns is increased to improve pixel count, then quantity of substance is improved, but the number of required buffer stages increases leading to larger layout area
Solution Approach 1:
The patent segments the clock distribution for increased column counts into hierarchical stages. The first stage handles initial distribution to groups of columns, the second stage distributes within groups, and the third stage provides final signal conditioning. This segmentation allows supporting high pixel counts (4000+ columns) without linearly increasing the number of buffer stages, thereby controlling layout area while maintaining quantity.
Solution Approach 2:
The patent introduces hierarchical dimensioning to the clock distribution system, organizing buffer and inverter stages to efficiently serve increased column counts. This dimensional organization allows the system to scale to high pixel counts without proportionally increasing layout area, as each hierarchical stage serves multiple columns through controlled fan-out.
Data Source
AI summary
A solid-state imaging device includes: a column comparison circuit which compares a pixel signal with ramp waves and detects a timing at which the pixel signal and the ramp waves match; a counter circuit which is disposed for each of the pixel columns and measures the timing in the column comparison circuit by being supplied with a clock signal; and M first inverters which are equidistantly connected in series, wherein the counter circuit belongs to one of M groups corresponding to each of the M first inverters disposed in the upper clock stage, the odd-numbered group has second inverters disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group, and the even-numbered group has buffers disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group.