Imaging Device Control Circuit Timing for A/D Conversion Noise
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Solution Overview
Problem
During analog-to-digital (A/D) conversion in imaging devices, variations in reference and analog signals due to control pulses reduce the accuracy of the conversion, affecting image quality by introducing noise and crosstalk, which degrades the quality of images captured.
Innovation Solution
An imaging device configuration that includes a pixel circuit, amplification circuit with a feedback capacitor and switching element, a sample and hold circuit, A/D conversion circuit, memory circuit, and a control circuit to manage control signals such that they do not overlap with the A/D conversion or reading periods, preventing power supply variations and feedthrough noise from affecting the conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If control pulses are generated during A/D conversion period, then the operation speed is improved, but the accuracy of A/D conversion deteriorates due to variations in reference signal and analog signal
Solution Approach 1:
The control signal is designed to complete its rise and fall transitions before the A/D conversion period begins. Specifically, the control signal rises before the sampling period and falls before the A/D conversion period, ensuring that no transitions occur during conversion. This preliminary timing arrangement prevents power supply variations and feedthrough noise from affecting the conversion accuracy while allowing high-speed operation.
2Speed
If control signal transitions occur during reading period, then the processing speed is improved, but the digital signal reading accuracy deteriorates
Solution Approach 1:
The control signal is timed to complete its fall transition before the reading period begins. The control signal falls at a timing that ensures the A/D conversion is complete and the digital signal is stable before reading operations start. This prevents control signal transitions from interfering with the reading process while maintaining high processing speed.
3Productivity
If switching element operates frequently to maintain high frame rate, then the dynamic range is improved, but noise and crosstalk increase
Solution Approach 1:
The control signal is designed with different timing characteristics for different operational phases. The rise timing is optimized for the sampling period while the fall timing is optimized for the A/D conversion period. This localized optimization of control signal timing in different phases reduces feedthrough noise and crosstalk during critical conversion and reading operations while maintaining high frame rates through efficient switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances image quality by suppressing noise and crosstalk, maintaining high frame rates and dynamic ranges while preventing power supply variations from interfering with the A/D conversion and reading processes.
Implementation Method 1
a pixel circuit configured to generate an analog signal in accordance with a quantity of incident light
Implementation Method 2
an amplification circuit including a feedback capacitor and a switching element for resetting the feedback capacitor
Data Source
AI summary
An imaging device includes a pixel circuit configured to generate an analog signal; an amplification circuit including a feedback capacitor and its reset switching element; a sample and hold circuit for the amplified analog signal; an A/D conversion circuit for the analog signal held in the sample and hold circuit; a memory circuit configured to store the digital signal; a reading circuit configured to read the digital signal stored in the memory circuit; and a control circuit configured to perform a rise and a fall of the control signal such that the rise and the fall do not overlap a conversion period of the analog signal by the A/D conversion circuit and do not overlap a reading period of the digital signal by the reading circuit, when the switching element is off during a sampling period of the analog signal.