Solid-State Imaging Device Adjusting Circuit Reducing Control Signal Amplitude
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Solution Overview
Problem
Conventional solid-state imaging devices face limitations in reducing the logic swing of control pulses for switching transistors, leading to insufficient reduction in analog-to-digital (AD) conversion time and hence, fail to achieve a high frame rate.
Innovation Solution
A solid-state imaging device with a pixel unit, AD converting units, and an adjusting circuit that controls the AD converting units simultaneously by reducing the amplitude or delaying the control signal, allowing for synchronized AD conversion across columns, thereby reducing the overall AD conversion time and enhancing frame rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the amplitude of control signal is reduced to synchronize AD conversion across columns, then AD conversion time is reduced and frame rate is improved, but the switching transistors may not reliably turn on/off
Solution Approach 1:
An adjusting circuit is introduced as an intermediary between the control unit and AD converting units. This circuit reduces the amplitude of control signals before they reach the switching transistors, enabling reliable operation with smaller voltage swings that allow synchronized AD conversion across all columns without compromising transistor switching reliability
Solution Approach 2:
The adjusting circuit dynamically adjusts the amplitude parameter of control signals. By reducing the voltage amplitude to an optimal level, the system achieves synchronized AD conversion across columns while maintaining sufficient signal strength for reliable transistor switching, thus improving frame rate without sacrificing reliability
2Loss of time
If control signals are supplied simultaneously to all AD converting units, then AD conversion time is reduced, but timing synchronization becomes difficult to maintain
Solution Approach 1:
The adjusting circuit serves as a timing intermediary that receives control signals from the control unit and distributes them to all AD converting units. This intermediary ensures that all units receive control signals at the same time and begin AD conversion simultaneously, maintaining precise timing synchronization across the entire array
Solution Approach 2:
The adjusting circuit creates equipotential timing conditions across all columns by ensuring that control signals reach all AD converting units simultaneously. This equalizes the starting conditions for AD conversion across the array, enabling synchronized operation and reducing total conversion time
Data Source
AI summary
A solid-state imaging device includes: a pixel unit which includes a plurality of pixels arranged in rows and columns and which generates pixel signals according to an amount of incident light; a column analog-to-digital converter (ADC) which is disposed for each of the columns of the pixel unit and which performs digital conversion on each of the pixel signals output from the pixels in the column; a timing control unit which generates a control signal for controlling the digital conversion performed by the column ADC; and a logic swing and delay adjusting circuit which is disposed in a signal path for supplying the control signal from the timing control unit to the column ADC and which at least either reduces an amplitude of the control signal or delays the control signal.