Solid-State Imaging Device Column ADC Parallel Readout
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Solution Overview
Problem
Conventional solid-state imaging devices face challenges in achieving higher operating speeds while maintaining precision and stability as the number of pixels increases, particularly in analog circuits, making it difficult to meet growing demands for faster operation.
Innovation Solution
A solid-state imaging device configuration that includes a pixel unit with AD conversion circuits in each column, memory circuits with multiple memories for storing and transferring digital signals in parallel, and horizontal transfer circuits to interchange memory roles, allowing continuous and parallel processing of digital signals across different rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of pixels is increased to meet growing demands, then the imaging capability is improved, but the operating speed deteriorates due to challenges in analog circuits
Solution Approach 1:
The imaging device divides the pixel array into multiple columns, with each column having its own independent ADC circuit. This segmentation allows parallel processing of signals from different columns, thereby maintaining high operating speed even as the total number of pixels increases.
Solution Approach 2:
The patent transitions from sequential row-by-row readout to a two-dimensional parallel readout architecture where multiple columns are processed simultaneously. This dimensional change in the data flow architecture enables the system to handle increased pixel counts without proportionally increasing readout time.
2Productivity
If the operating speed of ADC conversion circuits is increased to achieve higher-speed operation, then the productivity is improved, but the precision and stability deteriorate
Solution Approach 1:
By providing separate ADC circuits for each column rather than sharing a single ADC, the system achieves parallel conversion capability. This segmentation allows the imaging device to increase effective operating speed through parallel processing while each individual ADC can operate at moderate speeds, maintaining precision and stability.
3Productivity
If multiple ADCs are provided for each column to achieve higher-speed operation, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The patent implements a moderate level of segmentation by providing one ADC per column, which balances parallelism with complexity. This is more efficient than providing multiple ADCs per column while still achieving significant speedup through parallel processing across columns.
Solution Approach 2:
Each column's ADC circuit is designed with the same functional architecture, allowing for standardized fabrication and reducing overall system complexity despite the presence of multiple ADCs. The uniform design across columns enables reuse of the same circuit blueprint, simplifying manufacturing and testing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the effective operating speed of the solid-state imaging device without increasing the operating speed of AD conversion circuits, enabling continuous and high-speed digital signal output while maintaining precision and stability.
Implementation Method 1
each of the pixel circuits outputting an analog signal by performing photoelectric conversion
Data Source
AI summary
A solid-state imaging device includes: a plurality of pixels arranged in a matrix, the matrix defining columns of the pixels, and each of the pixels outputting an analog signal by performing photoelectric conversion; an analog-digital converter provided for each of columns which sequentially converts a plurality of analog signals outputted from the pixels in a column into a plurality of digital signals; a memory circuit provided for each column which includes memories and performs, in parallel, a process of storing a one of the digital signals in one of the memories and a process of outputting another of the digital signals previously stored in another of the memories; and data buses connected to the memory in each column.