Solid-State Imaging Device Column Memory Segmentation

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Solution Overview

Problem

Conventional solid-state imaging devices experience horizontal stripe noise, also known as streak, when capturing high-intensity objects due to increased current flow and voltage drops in the power line, which affects image quality.

Innovation Solution

The implementation of a block configuration for column memories and unit pixel groups, featuring memory and pixel signal lines with shared selection switches and transistors, reduces parasitic capacitance and current consumption, thereby minimizing voltage drops and enhancing signal transfer speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If pixel information is stored into the memory unit at higher speed, then productivity is improved, but horizontal stripe noise increases due to increased current flow and voltage drops

Engineering Contradiction:
Improvestorage speedVSAvoidhorizontal stripe noise
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The memory unit is divided into multiple column memory blocks, each connected to a dedicated memory signal line. This segmentation reduces the total capacitance on each signal line by limiting the number of connected memory cells, thereby reducing current consumption and voltage drops during high-speed operations while maintaining storage speed productivity

Inventive Principle:
Principle #1Segmentation

2Device complexity

If a conventional memory configuration is used, then device complexity is reduced, but parasitic capacitance increases causing voltage drops in power lines

Engineering Contradiction:
Improvememory configurationVSAvoidpower line voltage drop
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The memory unit is segmented into multiple column memory blocks with dedicated memory signal lines. This segmentation reduces parasitic capacitance on each signal line by limiting the number of connected memory cells, thereby reducing current consumption and voltage drops in power lines during high-speed operations

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each column memory block is assigned a dedicated memory signal line with optimized local characteristics. This local quality approach ensures that each block operates with minimal interference and reduced capacitance, improving overall system performance while maintaining manageable device complexity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses horizontal stripe noise and allows for high-speed signal transfer, improving image quality by reducing power line voltage drops and parasitic capacitance.

Implementation Method 1

each of the unit memories includes a write transistor, a capacitor, and a read transistor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9736412B2Solid-state imaging device, method for driving solid-state imaging device, and imaging device
Publication Date: 2017.08.15 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US9736412B2 patent drawing
  • US9736412B2 patent drawing
  • US9736412B2 patent drawing

AI summary

A solid-state imaging device includes: a pixel unit in which a plurality of unit pixels is arranged in rows and columns, the unit pixels performing photoelectric conversion of incident light to generate pixel information; and a secondary memory unit in which a plurality of unit memories is arranged in rows and columns, the unit memories holding the pixel information, wherein each of the columns in the secondary memory unit includes, as a unit memory block, the unit memories in the column, the secondary memory unit includes: a memory signal line provided for each of the columns in the memory unit; and a selection transistor provided between the unit memory block and the memory signal line, and shared by the plurality of unit memories in the unit memory block.