Solid-State Imaging Device Dummy Pattern CMP Planarization
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Solution Overview
Problem
Conventional solid-state imaging devices face a global level difference on the surface of the interlayer insulation film due to varying polishing rates across the pixel, peripheral circuit, and scribe lane regions, leading to shading and deteriorated light sensitivity and incident angle characteristics.
Innovation Solution
The method involves forming dummy patterns in the peripheral circuit and scribe lane regions to create a uniform average height of the interlayer insulation film surface before Chemical Mechanical Polishing (CMP), using a dummy protection insulation film and optionally a dummy gate electrode to match the height of the pixel region, thereby equalizing polishing rates across regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased and chip size is reduced, then imaging resolution is improved, but wiring microfabrication becomes more difficult due to global level difference
Solution Approach 1:
Dummy patterns are formed in advance in the peripheral circuit region and scribe lane region to adjust the average height of the interlayer insulation film. This preliminary action ensures that when wiring is fabricated through CMP, the global level difference is eliminated, making microfabrication easier and enabling higher imaging resolution with smaller chip sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the global level difference, enhancing the flatness of the interlayer insulation film, improving light sensitivity, and achieving higher resolution and miniaturization of the image sensor.
Implementation Method 1
a technology for planarizing a surface of an interlayer insulation film such as a CMP (Chemical Mechanical Polishing) is utilized
Data Source
AI summary
A method for fabricating a solid-state imaging device comprises: a step of forming a photodiode protection insulation film 6a; a step of forming a dummy protection insulation film 6c corresponding to the photodiode protection insulation film 6a both in the peripheral circuit region 1b and the scribe lane region 1c; and a step of forming an interlayer insulation film 9 for covering all three regions of a pixel region 1a in which pixels and the photodiode protection insulation film 6a are formed, a peripheral circuit region 1b in which a driving circuit and the dummy protection insulation film 6c are formed, and a scribe lane region 1c in which the dummy protection insulation film 6c is formed, wherein the dummy protection insulation film 6c causes an average height of a surface of the interlayer insulation film 9 included in each of the peripheral circuit region 1b and the scribe lane region 1c to be close to an average height of a surface of the interlayer insulation film 9 included in the pixel region 1a, before a CMP is performed on an entirety of the surface thereof.