Solid-State Imaging Device Hierarchical Vertical Output Line Architecture
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Solution Overview
Problem
The high parasitic capacitance of pixel select transistors connected to the vertical output line in solid-state imaging devices hinders the increase of readout rate, as existing methods lack a practical implementation for hierarchizing the vertical output line effectively.
Innovation Solution
A solid-state imaging device is designed with a hierarchical structure where pixel circuits are grouped into blocks connected to sub-vertical output lines, which are then connected to a main vertical output line via block select circuits, reducing the load capacitance and enabling high-speed pixel signal readout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel select transistors are connected to the vertical output line, then pixel signals can be selected and output, but the parasitic capacitance increases and readout rate cannot be increased
Solution Approach 1:
The vertical output line is divided into a main vertical output line and multiple sub vertical output lines. Each sub vertical output line is connected to a group of pixel select transistors, while the main vertical output line connects to the output amplifier. This segmentation distributes the parasitic capacitance load across multiple sub lines rather than concentrating it on a single vertical output line, enabling higher readout rates.
2Productivity
If the vertical output line is divided into main and sub lines with switches, then the load capacitance is reduced, but the device complexity increases
Solution Approach 1:
Multiple sub vertical output lines are merged into a single main vertical output line through selective switching. The block select circuits control the connection between sub lines and the main line, allowing multiple signal paths to be combined onto one line at a time. This merging approach reduces the number of amplifiers needed while maintaining high readout speed through the hierarchical structure.
3Ease of operation
If block select circuits are provided for each first vertical output line, then pixel signal selection is improved, but the number of components and circuit complexity increases
Solution Approach 1:
The block select circuits serve multiple functions: they select which sub vertical output line is active, control the timing of signal transfer to the main line, and manage the hierarchical structure. By making these circuits multi-functional, the patent reduces the need for separate dedicated components for each function, thereby reducing overall complexity while maintaining ease of pixel signal selection.
Data Source
AI summary
A solid-state imaging device includes a plurality of pixels arranged in a matrix, wherein one pixel of the plurality of pixels is arranged in one unit pixel region of a plurality of unit pixel regions, a plurality of sub vertical output lines, each of which outputs pixel signals from the plurality of pixels in the same pixel column, and a plurality of block select circuits provided in one-to-one correspondence with the plurality of sub vertical output lines. A load capacitance connected to a main vertical output line is reduced by connecting the plurality of sub vertical output lines and the main vertical output line via the plurality of block select circuits. This makes high-speed pixel signal readout possible.