Solid-State Imaging Device Impurity Region Alignment

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Solution Overview

Problem

Existing solid-state imaging devices face challenges in controlling the extension of N-type impurity regions under transfer gate electrodes, leading to potential well and barrier formation during charge transfer, resulting in charge transfer failures at low voltages.

Innovation Solution

A solid-state imaging device structure is developed with specific impurity region configurations and manufacturing methods that include forming a second conductivity type fifth impurity region, a third impurity region in contact with the gate insulating film, and a second impurity region extending under the gate electrode from the first end portion, ensuring self-aligned formation and controlled impurity concentrations to prevent potential well and barrier formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the extension amount of the N-type impurity region under the transfer gate electrode is increased to avoid potential barrier formation, then charge transfer reliability is improved, but a potential well is formed causing charge transfer failure

Engineering Contradiction:
Improvecharge transfer reliabilityVSAvoidpotential well formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating different impurity concentration zones within the N-type impurity region. Specifically, it forms a first N-type impurity region with higher concentration and a second N-type impurity region with lower concentration, where the second region extends under the transfer gate electrode. This local variation in impurity concentration allows the structure to prevent potential barriers at the interface while avoiding potential well formation in the charge transfer path, thus resolving the contradiction between reliability and harmful factor generation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs parameter changes by systematically varying the impurity concentration parameter across different regions. The first N-type impurity region has a higher impurity concentration to ensure good contact and prevent barriers, while the second N-type impurity region has a lower concentration to extend under the gate without forming potential wells. This controlled parameter change enables the structure to simultaneously achieve reliable charge transfer and avoid charge transfer failures.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If the extension amount of the N-type impurity region under the transfer gate electrode is decreased to avoid potential well formation, then charge transfer stability is improved, but a potential barrier is formed causing charge transfer failure

Engineering Contradiction:
Improvecharge transfer stabilityVSAvoidpotential barrier formation
Core Design Contradiction:
Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

The patent uses local quality by forming a P-type impurity region specifically at the interface between the N-type impurity region and the gate electrode. This localized P-type region acts as a buffer zone that prevents potential barrier formation without requiring extensive extension of the N-type region under the gate. The P-type region is positioned precisely where the barrier would form, providing local correction to the potential distribution and ensuring stable charge transfer.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces a P-type impurity region as an intermediary between the N-type impurity region and the gate electrode structure. This intermediary layer mediates the electrical potential transition, preventing the formation of potential barriers that would otherwise occur at the N-type/gate interface. The P-type region serves as a buffer that facilitates smooth charge transfer while maintaining stability, thus resolving the contradiction between stability and barrier formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If the N-type impurity region is extended under the transfer gate electrode to ensure good contact, then manufacturing precision is improved, but alignment accuracy becomes difficult to control

Engineering Contradiction:
Improveimpurity region alignmentVSAvoidalignment control complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the N-type impurity region into two distinct parts: a first N-type impurity region with higher concentration and a second N-type impurity region with lower concentration. This segmentation allows each region to serve a specific function - the first region ensures good contact with precise alignment, while the second region extends under the gate with controlled concentration to maintain alignment accuracy. The segmentation reduces the complexity of controlling overall alignment by breaking it into manageable zones with different requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses local quality by assigning different impurity concentrations to different spatial regions of the N-type impurity structure. The first N-type region has higher concentration for precise contact alignment, while the second N-type region has lower concentration for extended coverage under the gate. This local differentiation in quality enables manufacturing precision to be maintained in critical areas while reducing alignment control complexity in extended areas.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9818789B2Solid-state imaging device and manufacturing method thereof
Publication Date: 2017.11.14 SEIKO EPSON CORP
  • US9818789B2 patent drawing
  • US9818789B2 patent drawing
  • US9818789B2 patent drawing

AI summary

A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P−-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N−-type impurity region that is in contact with the P−-type impurity region and the gate insulating film, and an N−−-type impurity region that surrounds at least a portion of the N−-type impurity region in plan view.