Solid State Imaging Device Impurity Regions Dark Current
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Solution Overview
Problem
CMOS sensors face issues with dark current generation and potential barrier formation in the transfer path for signal charges, leading to poor transfer efficiency and backflow of signal charges.
Innovation Solution
A solid state imaging device is designed with specific impurity regions and their configurations to reduce dark current and suppress potential barrier formation, including a third impurity region on top of the second impurity region and a fourth impurity region between the second impurity region and the gate insulation film, with the fifth impurity region extending from the gate insulation film to the second impurity region, to create a smooth transfer path and prevent backflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a diffusion layer of the first conductivity type having a high concentration is formed on the diffusion region of the second conductivity type, then dark current is reduced, but a potential barrier is formed in the transfer path causing poor transfer efficiency
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones within the impurity region. Specifically, a first impurity region with first concentration and a second impurity region with second concentration (different from the first) are formed in different areas. This allows the high concentration zone to suppress dark current while the optimized concentration distribution prevents potential barrier formation in the transfer path, thus resolving the contradiction between dark current reduction and transfer efficiency.
Solution Approach 2:
The patent changes the impurity concentration parameter by forming multiple impurity regions with different concentrations. The first impurity region has a first impurity concentration while the second impurity region has a second impurity concentration. By controlling and varying these concentration parameters in different spatial locations, the patent achieves both dark current suppression and maintained transfer efficiency without forming potential barriers.
2Quantity of substance
If a diffusion layer of the first conductivity type having a high concentration is formed on the diffusion region, then residual charges are reduced, but signal charges may flow backward causing backflow
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones within the impurity region. Specifically, a first impurity region with first concentration and a second impurity region with second concentration (different from the first) are formed in different areas. This allows the high concentration zone to suppress dark current while the optimized concentration distribution prevents potential barrier formation in the transfer path, thus resolving the contradiction between dark current reduction and transfer efficiency.
Solution Approach 2:
The patent changes the impurity concentration parameter by forming multiple impurity regions with different concentrations. The first impurity region has a first impurity concentration while the second impurity region has a second impurity concentration. By controlling and varying these concentration parameters in different spatial locations, the patent achieves both dark current suppression and maintained transfer efficiency without forming potential barriers.
Data Source
AI summary
A solid state imaging device according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film that is located on the semiconductor layer; a gate electrode that is located on the gate insulation film; a first impurity region of a second conductivity type that is located at least in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type that is located in a region extending across a second end portion that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type that is located on top of the second impurity region at a position outside the gate electrode on the second end portion side, and is in contact with the second impurity region.