Solid-State Imaging Device Impurity Region Segmentation
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Solution Overview
Problem
Existing solid-state imaging devices face challenges in controlling the extension of N-type impurity regions under transfer gate electrodes, leading to potential well or barrier formation during charge transfer, resulting in charge transfer failures, especially at low voltages.
Innovation Solution
A solid-state imaging device structure is developed with specific impurity region configurations and manufacturing methods that include forming a second conductivity type fifth impurity region in contact with the gate insulating film and a second impurity region extending under the gate electrode from the first end portion, preventing potential well and barrier formation by ensuring self-aligned impurity region formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the extension amount of the N-type impurity region under the transfer gate electrode is increased to avoid potential barrier formation, then charge transfer reliability is improved, but a potential well is formed causing charge transfer failure
Solution Approach 1:
The impurity region is divided into multiple segments with different conductivity types and impurity concentrations. Specifically, a first conductivity type first impurity region, a first conductivity type second impurity region, a second conductivity type third impurity region, a second conductivity type fifth impurity region, and a second conductivity type fourth impurity region are formed in sequence. This segmentation allows each region to perform its specific function in controlling the potential distribution, preventing both potential barriers and potential wells from forming during charge transfer.
2Object-generated harmful factors
If the extension amount of the N-type impurity region under the transfer gate electrode is decreased to avoid potential well formation, then potential well-related charge transfer failure is prevented, but a potential barrier is formed causing charge transfer failure
Solution Approach 1:
Different regions of the impurity structure are assigned different local qualities in terms of conductivity type and impurity concentration. The first conductivity type first impurity region has higher impurity concentration, the first conductivity type second impurity region has intermediate concentration, and the second conductivity type third impurity region has lower concentration. This local quality differentiation creates an optimized potential distribution that prevents both potential barriers and potential wells, ensuring reliable charge transfer.
3Ease of manufacture
If the impurity region configuration is simplified for ease of manufacture, then manufacturing complexity is reduced, but control over potential well and barrier formation becomes difficult
Solution Approach 1:
The gate electrode and gate insulating film are formed first as a preliminary structure, and then the multiple impurity regions are formed in sequence using self-aligned processes. The first conductivity type first impurity region is formed outside the gate electrode, followed by the first conductivity type second impurity region extending under the gate electrode, then the second conductivity type third impurity region, the second conductivity type fifth impurity region in contact with the gate insulating film, and finally the second conductivity type fourth impurity region. This preliminary action approach ensures precise control over the extension amounts and positions of each impurity region while maintaining manufacturing feasibility.
Data Source
AI summary
A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P−-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N−-type impurity region that is located in the semiconductor layer under the P−-type impurity region and includes a portion that is under the pinning layer, and an N−-type impurity region that is in contact with the gate insulating film and the P−-type impurity region and is located so as to surround the N−-type impurity region in plan view.