Solid-State Imaging Device kTC Noise Reduction
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Solution Overview
Problem
Current stacked solid-state imaging devices face challenges in reducing kTC noise, especially when unit pixels consist of only three transistors, as they cannot completely cancel out kTC noise due to capacitive coupling and incomplete charge transfer.
Innovation Solution
A solid-state imaging device design that includes a semiconductor substrate with pixels having a photoelectric converting film, a pixel electrode, a transparent electrode, a charge storage portion, an amplifier transistor, a reset transistor, and a selection transistor, where specific voltage control is applied to the selection and reset transistors to manage channel resistance and noise cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If correlated double sampling is used to cancel kTC noise, then noise reduction is improved, but complete cancellation is not achieved due to incomplete charge transfer between photoelectric conversion unit and semiconductor substrate
Solution Approach 1:
The patent extracts the harmful kTC noise component by introducing a dedicated reset transistor that completely disconnects the photoelectric conversion unit from the signal charge storage node during reset operation. This separation allows independent reset of the storage node without being constrained by the physical connection to the photoelectric conversion unit, enabling complete noise cancellation.
Solution Approach 2:
The reset transistor acts as an intermediary element between the photoelectric conversion unit and the signal charge storage node. By controlling this intermediary component, the patent enables complete charge transfer and noise cancellation that cannot be achieved through direct connection alone, resolving the limitation of conventional correlated double sampling.
2Area of stationary object
If unit pixel size is reduced to three transistors for size reduction, then device area is reduced, but kTC noise reduction capability deteriorates due to insufficient transistors for complete noise cancellation
Solution Approach 1:
The patent merges the reset function with the signal charge storage and readout functions within a unified three-transistor configuration. The reset transistor is integrated into the same pixel circuit as the photoelectric conversion unit and signal charge storage node, allowing complete noise cancellation without requiring separate dedicated noise reduction circuits, thus achieving both small size and effective noise reduction.
Solution Approach 2:
The patent changes the operational parameters of the three-transistor circuit by applying specific voltage sequences to the reset transistor gate. By controlling the timing and voltage levels applied to the reset transistor, the circuit achieves complete charge transfer and noise cancellation despite the reduced transistor count, maintaining noise reduction capability while minimizing pixel area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces kTC noise even in unit pixels with three transistors by optimizing the voltage control of the selection and reset transistors, forming a cascode amplifier that boosts gain and accommodates the bandwidth of kTC noise, thereby enhancing noise reduction.
Implementation Method 1
a photoelectric converting film
Data Source
AI summary
A solid-state imaging device includes pixels each including: a charge storage portion; an amplifier transistor having a gate connected to the charge storage portion; a selection transistor having a source connected to a source of the amplifier transistor and a drain connected to a column signal line; and a reset transistor having a source connected to the charge storage portion and a drain connected to the column signal line, and further includes a control unit which applies to a gate of the selection transistor a first voltage to place the selection transistor in a conductive state and applies to a gate of the reset transistor a second voltage to place the reset transistor in a non-conductive state in a pixel signal readout period, and applies to the gate of the selection transistor a voltage intermediate between the first voltage and the second voltage in a charge storage portion resetting period.