Imaging Device Multi-Level Signal Line Shielding
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Solution Overview
Problem
Stacked imaging devices face challenges in reducing noise levels, particularly due to kTC noises and parasitic capacitance, which cannot be adequately addressed by simple correlated double sampling, and traditional noise reduction methods often increase the device area.
Innovation Solution
The imaging device incorporates a multi-level signal line as a shield wire between interconnections to reduce parasitic capacitance coupling, using it to shield the charge storage region from noise, while maintaining a compact design by avoiding the need for additional shield wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a shield wire is added between interconnections to reduce parasitic capacitance coupling, then noise levels are reduced, but device area increases
Solution Approach 1:
The patent combines the shield wire function with the existing multi-level signal line by applying multiple voltage levels to it. Instead of adding a separate shield wire, the same conductive structure serves both as a signal transmission line and as a noise shield, thereby reducing parasitic capacitance coupling without increasing device area.
Solution Approach 2:
The multi-level signal line is given dual functionality: it transmits pixel signal data while simultaneously acting as a shield wire to reduce parasitic capacitance coupling between adjacent interconnections. This multi-functionality eliminates the need for dedicated shield wires and prevents area increase.
2Object-affected harmful factors
If correlated double sampling is used to reduce kTC noises, then noise levels are reduced, but it cannot adequately address parasitic capacitance issues
Solution Approach 1:
The patent introduces a multi-level voltage signal as an intermediary mechanism to actively control and manage parasitic capacitance effects. By dynamically adjusting the voltage levels on the signal line, the parasitic capacitance coupling is actively suppressed, complementing the correlated double sampling technique and providing comprehensive noise reduction.
3Object-affected harmful factors
If additional shield wires are added to reduce parasitic capacitance, then coupling noise is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the shield wire function with the existing signal line structure by utilizing multi-level voltage signaling. This combination eliminates the need for additional separate shield wire structures, thereby reducing manufacturing complexity while still achieving parasitic capacitance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces noise levels while preventing area increase, enhancing signal quality and maintaining a compact sensor size.
Implementation Method 1
a photoelectric converter that converts incident light into a signal charge
Implementation Method 2
reduce parasitic capacitance coupling, using it to shield the charge storage region from noise
Data Source
AI summary
An imaging device includes: a semiconductor substrate; pixels arranged two-dimensionally along row and column directions on the substrate; and one or more interconnection layers located on the semiconductor substrate, including a first signal line extending along the column direction and a second signal line to which a multi-level signal is applied. A first pixel includes: a photoelectric converter; a charge storage region; a first interconnection electrically connected to the charge storage region; and a first transistor that includes a first diffusion layer electrically connected to the first signal line and a second diffusion layer electrically connected to the second signal line and that outputs a signal to the first signal line. The first and second signal lines and the first interconnection are arranged in a first interconnection layer. The second signal line is located between the first interconnection and the first signal line, viewed perpendicularly to the substrate.