Solid-State Imaging Device Noise Reduction Multi-Stage Sample and Hold
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Solution Overview
Problem
Conventional solid-state imaging devices face challenges in reducing noise while achieving refinement and circuit area reduction, as high frequency noise is transferred through parasitic capacitance, making it difficult to maintain a constant current supply to amplifier transistors.
Innovation Solution
A solid-state imaging device with a column constant current source and multi-stage sample and hold circuits that stabilize the voltage at the gate terminals of load transistors, using a combination of holding capacitors and switch elements to reduce noise and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a larger holding capacitor is used to reduce high frequency noise, then noise reduction is improved, but circuit area increases
Solution Approach 1:
The patent divides the single holding capacitor into multiple smaller holding capacitors arranged in a matrix configuration. Each pixel column has its own holding capacitor, and multiple columns share capacitors in a structured manner. This segmentation achieves noise reduction equivalent to a large capacitor while using significantly less total circuit area.
Solution Approach 2:
The patent combines multiple holding capacitors to function collectively as a noise reduction system. By connecting multiple smaller capacitors in a matrix arrangement with shared readout circuitry, the system achieves the noise filtering effect of a large capacitor while optimizing area usage through resource sharing.
2Area of stationary object
If circuit area is reduced for refinement, then device size is improved, but noise reduction capability deteriorates
Solution Approach 1:
The patent segments the noise reduction function across multiple small holding capacitors distributed throughout the circuit rather than using one large capacitor. This allows the noise reduction capability to be maintained while the total area occupied by capacitor structures is significantly reduced, enabling further device refinement.
3Device complexity
If a single holding capacitor is used, then circuit simplicity is improved, but noise reduction effectiveness deteriorates
Solution Approach 1:
The patent merges multiple holding capacitors into a unified matrix structure with shared control and readout circuitry. While individual capacitors are small, their collective arrangement and coordinated operation provide enhanced noise reduction effectiveness, overcoming the limitations of a single capacitor while maintaining reasonable circuit complexity through systematic organization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively stabilizes the voltage at the gate terminals of load transistors, reducing noise and maintaining a constant current supply to amplifier transistors while minimizing circuit area, thereby enhancing image quality and reducing noise in the solid-state imaging device.
Implementation Method 1
a first multi-stage sample and hold circuit in which sample and hold circuits for sampling and holding the voltage are connected in multiple stages, the first multi-stage sample and hold circuit stabilizing the voltage which is supplied to the gate terminals of the plurality of load transistors
Implementation Method 2
a holding capacitor 613, based on a maintenance control signal from a maintenance control signal line
Data Source
AI summary
A solid-state imaging device according to the present invention includes: a pixel block in which pixels are arranged in a matrix; vertical common signal lines each provided for a corresponding one of columns of the plurality of pixels, and reads signals of pixels in the corresponding column; and a column constant current source which supplies a current to the vertical common signal lines, wherein the column constant current source includes: load transistors each having a source terminal and a drain terminal one of which is connected to one of the vertical common signal lines and the other of which is grounded; a constant voltage supply unit which supplies a voltage to gate terminals of the load transistors; and a voltage holding circuit in which sample and hold circuits are connected in multiple stages, and which stabilizes the voltage which is supplied to the gate terminals of the load transistors.